Allow some behavioral assignments to unresolved wires.

If the l-value is an unresolved wire, then elaboration can allow
the assignment as long as it is to bits that are not otherwise
driven. Handle this in some simple cases.
Handle proceedural writes to UWIRE objects.

The elaborator allows this only if it determines that the bits
that are procedural written are not also continuously written.
Account for force l-values that are uwires.
Handle packed structs as module outputs.
Fix broken search where member names accidentally match variables.
Start a sizer backend.
Collect some actual sizer statistics.
Rearrange counters to me more realistic

Instead of counting gate types, convert to gate count estimates
and some other interesting statistics. Also handling the descent
into child scopes.
More robust case statement synthesis

Handle the cases that the case statement carries complet sub-
statements. This is just a generalization of what is already
there.
Merge branch 'master' of git://github.com/steveicarus/iverilog