Revert "Revert "kernel: rng: Add IOCTL support to disable bus bandwidth""

This reverts commit 911fb8222bf5f4df424368a27b1c9f513db0a9d2

Change-Id: If9d4d8be7690c2cd7d4fffba084edb7247042dd0
qseecom: Copy userspace buffer into kernel space before dereferencing

ION memory is used for user space to kernel space data passing.
This is directly accessible in kernel. But, if the IOCTL is called
from user space without using User space library, then data might
be pointing to some other memory location, in which case, it would
not be possible to dereference this location in kernel & hence it
would be accessing invalid memory.

Change-Id: Ic50c76ee8b2a696dbb786fce3a68cdc782e15268
Signed-off-by: Hariprasad Dhalinarasimha <hnamgund@codeaurora.org>
msm: mdss: Replace enums with strings in panel dtsi

To make dtsi files more readable, enums or u32
values that referred to strings in the panel
dtsi files are replaced by strings.

Change-Id: I516358c7027fe9ed05541b56c2de47280a23baab
CRs-Fixed: 511801
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
ARM: dts: msm: correct ssd2080m panel commands and timing

Update ssd2080m panel on/off commands,vertical/horizontal
porch values and timing according to vendor's suggestion

CRs-fixed: 569455
Change-Id: Ia60bb8caf55ebbff96751f6b9706f9ef682428c7
Signed-off-by: Ray Zhang <rayzhang@codeaurora.org>
msm: mdss: Parse max bandwidth property from device tree

Maximum bandwidth on the AXI bus supported by MDSS is a hardware
capability that needs to be exposed to userspace process via
sysfs node for MDP composition decisions.

Change-Id: I60e74e96666ca97f21a9880f49a95c3264d01870
Signed-off-by: Sree Sesha Aravind Vadrevu <svadrevu@codeaurora.org>
Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
ARM: dts: msm: define max supported memory bandwidth for display

As display resolutions increase, the memory bandwidth requirement
increases as the number of layers supported increase. With these high
memory requirements it's not possible to sustain high memory bandwidth
requirement past a certain threshold without potentially underflowing.
These bandwidth thresholds are different across targets, define these
according to system level profiling results.

Change-Id: I360e59243ce483e77abf0ea9cd4944fd07d0f3dd
Signed-off-by: Sree Sesha Aravind Vadrevu <svadrevu@codeaurora.org>
cpufreq: Add Input Boost feature to the cpu-boost driver

On incoming input events boost the frequency of all online cpus
for at least input_boost_ms ms. This is accomplished by changing
the policy->min of all the online cpus to input_boost_freq.

Change-Id: Idb0ab75d68ae4ceff259cbbaaec1a9bb3bc871d3
Signed-off-by: Rohit Gupta <rohgup@codeaurora.org>
Revert "defconfig: 8226: Set ROW as the default block I/O scheduler"

This reverts commit 39db85c684d7c4a7dd8ea375c29a5ed502e98898.
The reverted commit was identified as the cause of the FS corruptions
observed on 8x26. The type of issues vary, but ultimately the symptom
is device is stuck in android screen internal reason could be file
system is mounted as RO or databases corruption or EROFS error or
EIO errors.

It's reverted till further annalists of the root cause of FS error.

Change-Id: I4d5d653abb5d9652f1baba560d8b444b739ab736
CRs-fixed: 581363
Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>
defconfig: msm: Enable KSM for msm8610

Kernel Samepage Merging (KSM) saves memory by merging
pages with the same content.

Change-Id: I89468761e03b08c4700d2aa0f7c8ccad45dd0550
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
android/lowmemorykiller: Account for total_swapcache_pages

The lowmemorykiller relies on NR_FILE_PAGES when measureing
the amount of reclaimable memory in the system.
However when swap is enabled swap cache pages are counted
in NR_FILE_PAGES, and swap cache pages aren't as reclaimable
in low memory as file cache pages. Therefore a large swap
cache can result in the lowmemorykiller not running and
an OOM occuring.

In order to ensure the lowmemorykiller properly evaluates the
amount of reclaimable memory don't count the swap cache pages.

Change-Id: I38239283e572f814b277c718eaf6be7f92abacbb
Signed-off-by: Liam Mark <lmark@codeaurora.org>
staging: zsmalloc: Ensure handle is never 0 on success

zsmalloc encodes a handle using the pfn and an object
index. On hardware platforms with physical memory starting
at 0x0 the pfn can be 0. This causes the encoded handle to be
0 and is incorrectly interpreted as an allocation failure.

This issue affects all current and future SoCs with physical
memory starting at 0x0. All MSM8974 SoCs which includes
Google Nexus 5 devices are affected.

To prevent this false error we ensure that the encoded handle
will not be 0 when allocation succeeds.

Change-Id: I5ad31712be4dd5105ebee81fa95927039c0f6935
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
tick: Dynamically set broadcast irq affinity

When a cpu goes to a deep idle state where its local timer is
shutdown, it notifies the time frame work to use the broadcast timer
instead.  Unfortunately, the broadcast device could wake up any CPU,
including an idle one which is not concerned by the wake up at all. So
in the worst case an idle CPU will wake up to send an IPI to the CPU
whose timer expired.

Provide an opt-in feature CLOCK_EVT_FEAT_DYNIRQ which tells the core
that is should set the interrupt affinity of the broadcast interrupt
to the cpu which has the earliest expiry time. This avoids unnecessary
spurious wakeups and IPIs.

[ tglx: Adopted to cpumask rework, silenced an uninitialized warning,
  massaged changelog ]

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: viresh.kumar@linaro.org
Cc: jacob.jun.pan@linux.intel.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: santosh.shilimkar@ti.com
Cc: linaro-kernel@lists.linaro.org
Cc: patches@linaro.org
Cc: rickard.andersson@stericsson.com
Cc: vincent.guittot@linaro.org
Cc: linus.walleij@stericsson.com
Cc: john.stultz@linaro.org
Link: http://lkml.kernel.org/r/1362219013-18173-3-git-send-email-daniel.lezcano@linaro.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

Change-Id: I6a880a39dd595526b80a6d72b88be74163513da9
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
cpuidle: make a single register function for all

The usual scheme to initialize a cpuidle driver on a SMP is:

	cpuidle_register_driver(drv);
	for_each_possible_cpu(cpu) {
		device = &per_cpu(cpuidle_dev, cpu);
		cpuidle_register_device(device);
	}

This code is duplicated in each cpuidle driver.

On UP systems, it is done this way:

	cpuidle_register_driver(drv);
	device = &per_cpu(cpuidle_dev, cpu);
	cpuidle_register_device(device);

On UP, the macro 'for_each_cpu' does one iteration:

        for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask)

Hence, the initialization loop is the same for UP than SMP.

Beside, we saw different bugs / mis-initialization / return code unchecked in
the different drivers, the code is duplicated including bugs. After fixing all
these ones, it appears the initialization pattern is the same for everyone.

Please note, some drivers are doing dev->state_count = drv->state_count. This is
not necessary because it is done by the cpuidle_enable_device function in the
cpuidle framework. This is true, until you have the same states for all your
devices. Otherwise, the 'low level' API should be used instead with the specific
initialization for the driver.

Let's add a wrapper function doing this initialization with a cpumask parameter
for the coupled idle states and use it for all the drivers.

That will save a lot of LOC, consolidate the code, and the modifications in the
future could be done in a single place. Another benefit is the consolidation of
the cpuidle_device variable which is now in the cpuidle framework and no longer
spread accross the different arch specific drivers.

Change-Id: I8f75188d5770871620f758c2973b74384ac570d5
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
ARM: mm: implement LoUIS API for cache maintenance ops

ARM v7 architecture introduced the concept of cache levels and related
control registers. New processors like A7 and A15 embed an L2 unified cache
controller that becomes part of the cache level hierarchy. Some operations in
the kernel like cpu_suspend and __cpu_disable do not require a flush of the
entire cache hierarchy to DRAM but just the cache levels belonging to the
Level of Unification Inner Shareable (LoUIS), which in most of ARM v7 systems
correspond to L1.

The current cache flushing API used in cpu_suspend and __cpu_disable,
flush_cache_all(), ends up flushing the whole cache hierarchy since for
v7 it cleans and invalidates all cache levels up to Level of Coherency
(LoC) which cripples system performance when used in hot paths like hotplug
and cpuidle.

Therefore a new kernel cache maintenance API must be added to cope with
latest ARM system requirements.

This patch adds flush_cache_louis() to the ARM kernel cache maintenance API.

This function cleans and invalidates all data cache levels up to the
Level of Unification Inner Shareable (LoUIS) and invalidates the instruction
cache for processors that support it (> v7).

This patch also creates an alias of the cache LoUIS function to flush_kern_all
for all processor versions prior to v7, so that the current cache flushing
behaviour is unchanged for those processors.

v7 cache maintenance code implements a cache LoUIS function that cleans and
invalidates the D-cache up to LoUIS and invalidates the I-cache, according
to the new API.

Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>

Change-Id: I561c3b187b5b87b25de07ea82a4ef73a42761e27
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: pm: idle-v7 clean up

Legacy platforms are not expected to use the mainline
anymore. Unsupported targets are MSM7X01A, MSM7X25,
MSM7X27, MSM7X30, QSD8X50, MSM8X60, MSM8960,MSM8930,
APQ8064, FSM9XXX, MSM9615, MSM8625, MSM9625, MSM7X27A.

Remove unused code in idle-v7 and its related files.

Change-Id: If1fbf9eead91d3410c5c5e75cb92824b110b1138
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: pm: cleanup spm code related to SAW2_V1

Code related to SAW2_V1 is removed. The relevant targets
are no more built on mainline.

Change-Id: Ie3f5a9f1dab0026b02e55384b6c620db774982b1
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: idle: Use ARM suspend/resume APIs to restore during warmboot

ARM generic cpu_suspend/resume APIs restore the necessary CP15 registers
to a known state when resuming from a reset state. Use of generic
suspend/resume APIs allows the msm warmboot code to not care about
restoring core registers used by ARM kernel. Also, the PM subsystem no
longer needs to allocate page table or uncached memory to save CPU
registers.

While at it convert most of the assembler code into respective C
function except for warmboot code that executes with MMU turned off.
Also, the idle subsystem no longer needs to manage a  page table or
uncached memory to save CPU registers.

Change-Id: I78a75d0a3c703390eec476199c7ca2786360e12a
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
ARM: Set CLK_EVT_FEAT_DYNIRQ flag memory mapped timers

Memory mapped timers are used as broadcast timers to wake up a core
across reset. CLK_EVT_FEAT_DYNIRQ ensures only the intended cores are
woken up instead of the default core that they are routed to, thereby
saving power.

Change-Id: I535faa0d1fd328fefe4422a6f362b17c94ab5b8e
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Revert "msm: lpm_levels: Adjust latency for Multi core cases"

This reverts commit b4e82b5c6ffac10efaae98213a57988ad424f2e7. The
performance and power benefits obtained with these changes were minimal
and hence removing this change.

Change-Id: I8495d4e7a669a5a0eb519e853eb0d45508a64c1a
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: pm: Rename pm-8x60.c to msm-pm.c

pm-8x60.c doesn't accurately reflect the current list of targets that
are supported. So renaming them to msm-pm.c to be more inline with the
msm chipsets.

Change-Id: Iefa8150885f8da136de7cba4a122ec901a171a02
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>