hdl/modules/fmc_adc_common/fmc_adc_data.vhd: add reset to FIFO

As of now, we are using an updated version of the general-cores
repository.

One of the modifications is the absence of the coregen stuff used
for generating FIFOs and RAMs. Now, Xilinx primitives are used for that
and a wrapper is provided to customize it.
modules/*/wb_fmc150/Manifest.py: Differentiate between synth and sim

The new version of hdlmake throws an error is an unavailable
variable is used in the Manifests. This was usually the case
in selecting modules for synthesis or simulation.
hdl/testbench/README: add Warning regarding the use of hdlmake
Merge branch 'hdlmake-fixes' into devel
hdl/syn/ml605/*_4ch_pcie/*: change to new hdlmake semantics

Added syn_tool variable to Manifest file and
a remote synthesis script based on the example
from hdlmake repository
hdl/ip_cores/etherbone-core: update submdule reference
hdl/syn/ml605/*dsp_fmc130m_4ch/*: change to new hdlmake semantics

Added syn_tool variable to Manifest file and
a remote synthesis script based on the example
from hdlmake repository
hdl/ip_cores/general-cores: update submodule reference

This was necessary, in order to fic a compilation error
as a function in Etherbone core was not defined
hdl/modules/fabric/*: updates from wr-cores repo

The Etherbone core uses some definitions that were
not present in out current copy of the fabric modules.
Now, we have updated these modules with the latest
master from wr-cores (3fbaa93c10)
hdl/modules/pcie/*: add new constant packages

Each PCIe component has its own package for defining
constants. On instantiation, one can include the specfic
package in order to get the constants for the PCIe
component. this is necessary when defining top-level
ports for PCIe.
hdl/top/*/*_dsp_fmc130m_4ch/*: use specific pcie package

Changed the constants defined in the top-level entity
for the ones defined in the bpm_pcie_ml605_pck.vhd
file. They are effectively the same, just defined in a
better place.
hdl/top/*/*_dsp_fmc130m_4ch/*: small cleanup

Removed misleading comments (e.g., old component declarations)
and unused signals/components
hdl/top/*/*_dsp_fmc130m_4ch/*: comment chipscope instantiation

By default, do not compile with chipscope. This is
now commented in the code.

Also, removed un_cross_top component declaration as
it was not used
hdl/modules/pcie/*: move PCIe componetns to specific folder

Now, each PCIe Core component (m605, k7, a7) has been
moved to its specific package. Also, the general package
was deleted as it was useless
hdl/modules/pcie/*: update packages with missing ports

There was missing the cs_n port from the top-level
entity
hdl/top/pcie/*: use PCIe component from package

PCIe component defeinitions were removed from
the TOP files. Intead they are now referenced
through the associated package
hdl/syn/pcie/Manifest.py: add syn_tool variable

The new version of hdlmake makes use of a
synthesis tool variable to indicate which
tool is being used (ISE or Quartus)
hdl/top/ml_605/*_pcie/*: reference ml605 PCIe package
hdl/top/ml_605/*dsp_fmc130m_4ch/*: reference ml605 PCIe package
hdl/Manifest.py: remove rffe_top module from Manifest

The RFFE module was not suppose to be listed
here, as it was moved to dsp-cores repository.
The complete removal of the rffe module will
come shortly