Adding Xilinx revision upgrade files to gitignore
Generating from 0 ejercicio_6
projects: updating git to not ignore some files and to ignore others. Adding syntax checker/corrector
ejercicio_6: Restarting from 0
ejercicio_6: Started ejercicio_6 once more. BSB project + pcore
ejercicio_6: Added pcore to design
ejercicio_6: I don't know how to make this stuff work. No idea =(
ejercicio_6: The module is now at least doing the additions, now I need to change the semple_logic module's logic