Allow the following
```scala
//Standard chisel
val clockA = new Clock(resetA);
//Create a clock domaine with clockA as clock and resetB as reset
val clockA_with_resetB = Clock(clockA,resetB);
//create clock domaine with current default clock (clk) and resetC
val clk_with_resetC = Clock(null,resetC);
```
The why is here : https://groups.google.com/forum/#!topic/chisel-users/dW3hLgie9us
Change default clock, Toplevel module as no reset automaticaly affected, now it's through top level default clock.
now you can have multiple clock domaine into top level module with register.
Additionaly you can connect a signal of your design to make a reset (local reset).
All seem good, I have checked verilog generated from lot of case, but line 363 of node.scala must be checked.