ARM: tegra: dvfs: Re-factor CPU alternative dvfs

Removed alternative frequencies table from dvfs structure, and
replaced it with table pointer to facilitate future support for
multiple alternative tables. Actually supported alternative dvfs
table (Tegra3 CPU cold zone table) is not changed.

Change-Id: Ia8c1d1f2dd450f0e48685e769ca925b8e6f5b57b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/104882
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: dvfs: Alter CPU dvfs on EDP events

Extended EDP processing of cpu up/down events with calls to alter CPU
dvfs table. This is in addition to already supported changing of CPU
dvfs on EDP thermal event. For now, added calls do not actually alter
the table.

Change-Id: I1cbf2c54eeca8dea1e7b6f4c65d8dbaf563a980e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/104883
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: dvfs: Separate Tegra3 single core dvfs table

On Tegra3 added mechanism to alter dvfs table between single and
multiple CPU cores. This mechanism is dormant since no single-core
table is available yet.

Change-Id: I63bd513bd5fd7347f64c88f46974cf7fac55c419
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/105508
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: decouple mode from flags

When doing LP2 on last standing CPU, we currently pass
"mode | flag" to a few functions as argument, with the
assumption that "mode" will be confined to lower 22 bits
in PMC_CTRL register and "flags" will occupy higher 10
bits. If "flags" grows downward or "mode" grows upward,
without this explicit knowledge, LP2 will break on the
last standing CPU. Therefore we need to decouple them.

Currently only "flags" part is being used when passed to
other subroutines, so use "flags" only.

Change-Id: I299c998145d81c17760bda8a0b56311fed553958
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/100358
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Conflicts:

	arch/arm/mach-tegra/pm.c
ARM: tegra: cpu: enable VDD_CPU rail before LP to G transition

When doing LP to G transition, it had a power up latency on VDD_CPU
rail. To reduce the latency, CPU_LP can trun on the VDD_CPU rail
before the LP to G transition.

Bug 930985

Change-Id: I087e185ea5aa90f309b8cafba9bc4bb7d3fc950c
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: http://git-master/r/93141
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Tested-by: Antti Miettinen <amiettinen@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
ARM: tegra: dvfs: Fix error checking of voltage

Fix error checking of predicted voltage. Also get rid of
maybe-uninitialized warning when using 4.6 toolchain.

Bug 949219
Bug 999222

Change-Id: I47553aba5a93c91bdd93cbf75081d69f92aec4dd
Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-on: http://git-master/r/108899
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
arm: tegra: Fix cpu governor change issue

It fixes the issue where cpu governor change
was inconsistent across platforms.

In T2x, AUTO HOTPLUG is disabled therefore we need
to store/restore gov for all online cpus across
LP0 cycle.

In T3x, AUTO HOTPLUG is enabled therefore storing/restoring
gov for Cpu0 across LP0 cycle. Cpu0 remains online in suspend
and resume.

bug 991081

Change-Id: I167654aa21e4832b3fdc40e3d388a4d3f984632b
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: http://git-master/r/105404
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Conflicts:

	arch/arm/mach-tegra/common.c
scheduler: compute time-average nr_running per run-queue

Compute the time-average number of running tasks per run-queue for a
trailing window of a fixed time period. The detla add/sub to the
average value is weighted by the amount of time per nr_running value
relative to the total measurement period.

Change-Id: I076e24ff4ed65bed3b8dd8d2b279a503318071ff
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit 3a12d7499cee352e8a46eaf700259ba3c733f0e3)
Reviewed-on: http://git-master/r/111635
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Tested-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
proc: enhance time-average nr_running stats

Add time-average nr_running to loadavg printout

Bug 958978

Change-Id: I5c6904efb52a86f4964eb66c1576fc91f60f5b1d
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 86f3642cc44a69d1e4798719bd9182cd6923f526)
Reviewed-on: http://git-master/r/111636
Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Tested-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
scheduler: Re-compute time-average nr_running on read

Re-compute time-average nr_running when it is read. This would
prevent reading stalled average value if there were no run-queue
changes for a long time. New average value is returned to the reader,
but not stored to avoid concurrent writes. Light-weight sequential
counter synchronization is used to assure data consistency for
re-computing average.

Change-Id: I8e4ea1b28ea00b3ddaf6ef7cdcd27866f87d360b
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 527a759d9b40bf57958eb002edd2bb82014dab99)
Reviewed-on: http://git-master/r/111637
Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Tested-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
ARM: tegra: power: Use runnable threads average for hotplug

Sample scheduler runnable threads average in auto-hotplug work
function and use it to determine the auto-hotplug target for number
of on-line cores. Use cpu up delay as sampling period, and enforce
down delay by checking last cpu configuration change time stamp.

Bug 958978

Change-Id: I4280a11d39914687e6ffaa6f38df594d10aedaa9
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 507e2ef5e4f09b23de2e924003dba259d3c8bc3c)
Reviewed-on: http://git-master/r/111638
Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Tested-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
arm: tegra: hotplug: tune runnable thread params.

Tuned the runnable threads threshold from 5/9/13 to 5/9/10 in order to improve performance

Bug 958978

Change-Id: I77abcd0077845517f2b5f7487c547f8a5157c2c7
Signed-off-by: Wen Yi <wyi@nvidia.com>
(cherry picked from commit 25a97f57661353fbb5ee40faed296befbf635178)
Reviewed-on: http://git-master/r/111639
Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Tested-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
arm: tegra: hotplug: modify down_delay

Modified the hot-plug governor down_delay to be 500ms instead of 2s

Bug 958978

Change-Id: I55b5a4994f8e4564879cfd206fc683ff6f32d9ac
Signed-off-by: Wen Yi <wyi@nvidia.com>
(cherry picked from commit dd477396f2762f871255fb9d0800431d7534754d)
Reviewed-on: http://git-master/r/111640
Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Tested-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
arm: tegra: modify hotplug balance threshold

Tuned the sensitivity level of the hot-plug governor's balancing algorithm to 60% from 75%

Bug 958978

Change-Id: I972ed908995e348e8b3b0afb8108c44b66c80eae
Signed-off-by: Wen Yi <wyi@nvidia.com>
(cherry picked from commit 07a69db5af4c971b2c2d161ee149580ab5b40633)
Reviewed-on: http://git-master/r/111641
Reviewed-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Tested-by: Sai Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
ARM: tegra: clock: Adjust Tegra3 cpu to emc ratio

On Tegra3 changed cpu rate threshold for maximum emc rate request from
750MHz to 925MHz. Adjusted cpu frequency table to provide entries close
to the new threshold for all Tegra3 skus.

Bug 998044
Bug 1003521

Signed-off-by: Alex Frid <afrid@nvidia.com>

Change-Id: I6e6df1958db9d55ad64cf35a5e9fe6ec74b8d4ea
Reviewed-on: http://git-master/r/106946
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
board/panel: remove pclk boost (causing screen tearing)
board/cpu-tegra3: make runnable thread as a compilation option
SCHEDULER: Autogroup patch group by current user android UID instead of task ID
board/tegra3_speedo: fix minor warnings
ARM: tegra: clock: Increase boost_up_threshold for AVP clock

Increase the boost_up_threshold to 85 for ULP audio

bug 1009849

Change-Id: I4b1b746f445f5c2804befa52ae95c69b6b467083
Signed-off-by: Vandana Salve <vsalve@nvidia.com>
Reviewed-on: http://git-master/r/114620
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>