atlys/clkgen: remove defparams
atlys: remove invalid DIVIDE(2) on BUFIO

Newer ISE (reported on >= 14.5) fail to build designs with
BUFIO2 that has the DIVIDE parameter set to 2.
The error message is:
"ERROR:PhysDesignRules:2502 - Issue with pin connections and/or
configuration on
   block:<dvi_gen0/sysclk_div>:<BUFIO2_BUFIO2>.  BUFIO2 has an invalid
setting
   of DIVIDE by 2. This setting is not supported. For more information
please
   see Answer Record 56113.
ERROR:Pack:1642 - Errors in physical DRC."

And, Answer Record 56113 states the following:
"In Spartan-6 FPGA, the BUFIO2 using the DIVIDE(2) applications can
occasionally enter a stuck state. Hence, it is not supported and an
alternative implementation needs to be used."

To get around this, instead of feeding the 100 MHz system clock
into dvi_gen, an already divided by 2 50MHz clock is used.
atlys: add timing constraints for dvi_gen CDC