[AVX512] Peel off an asm-only class from AVX512_masking_common.

No functional change.

This enables the generation of masking instructions that don't provide a
ISel pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219358 91177308-0d34-0410-b5e6-96231b3b80d8
[AVX512] Support mask register in MRMDestReg format

This is necessary for masking vextract*x4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219359 91177308-0d34-0410-b5e6-96231b3b80d8
[AVX512] Move DAG for all-zero node to X86VectorVTInfo

No functional change.

No change in X86.td.expanded except for the appearance of the new attributes.

The new attributes will be used in the subsequent patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219360 91177308-0d34-0410-b5e6-96231b3b80d8
[AVX512] Add asm-only support for vextract*x4 masking variants

These derive from the new asm-only masking definitions.

Unfortunately I wasn't able to find a ISel pattern that we could legally
generate for the masking variants.  The problem is that since the destination
is v4* we would need VK4 register classes and v4i1 value types to express the
masking.  These are however not legal types/classes in AVX512f but only in VL,
so things get complicated pretty quickly.  We can revisit this question later
if we have a more pressing need to express something like this.

So the ISel patterns are empty for the masking instructions and the next patch
will add Pat<>s instead to match the intrinsics calls with instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219361 91177308-0d34-0410-b5e6-96231b3b80d8
[AVX512] Intrinsics for vextract*x4

This adds the Pat<>'s for the intrinsics.  These are necessary because we
don't lower these intrinsics to SDNodes but match them directly.  See the
rational in the previous commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219362 91177308-0d34-0410-b5e6-96231b3b80d8
[AVX512] Rename AVX512_masking* to AVX512_maskable*

No functional change.

This is the current AVX512_maskable multiclass hierarchy:

                 maskable_custom
                    /       \
                   /         \
          maskable_common   maskable_in_asm
            /         \
           /           \
      maskable        maskable_3src

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219363 91177308-0d34-0410-b5e6-96231b3b80d8
Sink DwarfUnit::addSectionDelta into DwarfCompileUnit, the only place it's needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219364 91177308-0d34-0410-b5e6-96231b3b80d8
Fix typo in comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219365 91177308-0d34-0410-b5e6-96231b3b80d8
Remove getSubtargetImpl calls from FastISel, we can get it from
the MachineFunction where it's already cached.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219366 91177308-0d34-0410-b5e6-96231b3b80d8
Use both the cached TLI and the subtarget off of the DAG in
the DAG combiner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219367 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unnecessary include.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219368 91177308-0d34-0410-b5e6-96231b3b80d8
Sink DwarfDebug::addScopeRangeList down into DwarfCompileUnit

(& add a few accessors/make a couple of things public for this - it's a
bit of a toss-up, but I think I prefer it this way, keeping some more of
the meaty code down in DwarfCompileUnit - if only to make for smaller
implementation files, etc)

I think we could simplify range handling a bit if we removed the range
lists from each unit and just put a single range list on DwarfDebug,
similar to address pooling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219370 91177308-0d34-0410-b5e6-96231b3b80d8