[fft_core] Re-compiled FFT with new sma-wideband/mlib_devel@9bd9e185eb.
[fir_core] Temporarily removed the FIR altogether to help with timing.
[sma_corr] Added some user-defined area constraints that assist timing.

These can be used with the CASPER toolflow by setting the USER_UCF_PATH
to, in this case, "./sma_corr/pblocks".
[sma_corr] Lots of pipelines and other stuff added.

Too lazy to document most of it but so far we're at 1.2 million score
with fully routed design and zero hold errors. Compile takes roughly
7 hours.
[sma_corr] Added latency=3 pipelines after phase_0 and phase_1 registers.
[sma_corr] Added the cgain block arithmetic to the FFT area constraints.

Also, unignored the pblock directory in .gitignore.
[sma_corr] Replaced a Xilinx delay block with a CASPER pipeline in visibs/del.

This should help with meeting timing since this delay was being converted to a
SRL16 and creating large negative slack on that path.
[sma_corr] Set the cgain/gain_[0,1] block memory to use "Low Power".

They are previous set to use "Minimum Area" but this was changed with
the hope that it will help with meeting timing.
[sma_corr] Added area constraints for the visibility network outputs.
[sma_corr] Removed the digital tone and tone+noise in the source blocks.

This is hardly ever used and has been causing serious timing issues.
Revert "[sma_corr] Added area constraints for the visibility network outputs."

This reverts commit 08ec5a0a3bf6ce08a0b2e8587bfe3af1043a4f8d.
[sma_corr] Added pipeline=3 to the path from walsh table to cgain.

This is in an effort to reduce timing errors on these paths.
[cgain_core] Updated; replaced delays with pipelines; increased convert delay by 1.
[cgain_core] Changed the sin/cos lookup to use distributed instead BRAM.
Revert "[cgain_core] Changed the sin/cos lookup to use distributed instead BRAM."

This reverts commit 9f26a8e81322bc560f3a9fbb9bbc27d5d06227b0. This changes causes
MAP global optimization to just completely stall. No idea why.
[cgain_core] Set sin/cos lookup to auto for both memory type and optimiation.
[cgain_core] Increased sin/cos latency by 2.
[sma_corr] Added latency=3 pipeline to visibs/del.
[xeng_core] Updated CASPER blocks to sma-wideband/mlib_devel@a288ff33.

NOTE: I had to reorder inputs since the xeng output port order has apparently
changed. Specifically the sync_out is no longer on top but instead is port #3.
This change happened here specifically: ska-sa/mlib_devel@2ee01a69.
Revert "[xeng_core] Updated CASPER blocks to sma-wideband/mlib_devel@a288ff33."

This reverts commit 2e88d9f3898708b131450ede3e518d17b8e832e7.