renamed cam and bom files to hackeeg
updated packaging script for hackeeg
updated packaging scripts for hackeeg
updates to fix keepout errors; minor silkscreen improvements
minor changes to silkscreen
updated BOM to used JST through-hole connector for sync; fixed bottomlayer trace widths and routing
board now passed Advanced Circuits, SeeedStudio, and OSHPark design rules
updated board revision to 1.1.1; update package-seeed script
fixed silkscreen pin label bug - DAC0/1, CAN RX/TX
fixed Analog Input filter bug; added BIASINV signal to electrode connector and to unused power connector pin, with solder jumper; improved trace clearances
minor changes to BIASINV solder pad
switched to 24 position electrode connector (from 30); changed sync connector to 4-position (from 3 position); added BIASINV signal to sync connector; changed electrode connector and analog filtering schematic layout to be more readable
layout cleanup
changed solder mask (cream) stop to 1mil so stencils cut correctly using gerber2graphtec & graphtec cameo cutter
added stack-up.txt text file and added it to advanced circuits packaging script
added circular restrict polygons on AGND and DVDD layers, surrounding mounting holes - to avoid problems with Advanced Circuits plating the holes and causing short circuits
minor trace improvment near pin 21
changed inner layer (AGND and DVDD) polygon isolate clearance to 12 mils (from 0)
updated cam file to have better clearances; changed routing to avoid congestion and close traces on right edge of board toop and bottom
changed rest-rings to min 12mil and fixed all DRC errors