Add execution + assembler tests of AArch64 TRN Intrinsics.

	* gcc.target/aarch64/simd/vtrnf32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnf32.x: New file.
	* gcc.target/aarch64/simd/vtrnp16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnp16.x: New file.
	* gcc.target/aarch64/simd/vtrnp8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnp8.x: New file.
	* gcc.target/aarch64/simd/vtrnqf32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqf32.x: New file.
	* gcc.target/aarch64/simd/vtrnqp16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqp16.x: New file.
	* gcc.target/aarch64/simd/vtrnqp8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqp8.x: New file.
	* gcc.target/aarch64/simd/vtrnqs16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqs16.x: New file.
	* gcc.target/aarch64/simd/vtrnqs32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqs32.x: New file.
	* gcc.target/aarch64/simd/vtrnqs8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqs8.x: New file.
	* gcc.target/aarch64/simd/vtrnqu16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqu16.x: New file.
	* gcc.target/aarch64/simd/vtrnqu32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqu32.x: New file.
	* gcc.target/aarch64/simd/vtrnqu8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnqu8.x: New file.
	* gcc.target/aarch64/simd/vtrns16_1.c: New file.
	* gcc.target/aarch64/simd/vtrns16.x: New file.
	* gcc.target/aarch64/simd/vtrns32_1.c: New file.
	* gcc.target/aarch64/simd/vtrns32.x: New file.
	* gcc.target/aarch64/simd/vtrns8_1.c: New file.
	* gcc.target/aarch64/simd/vtrns8.x: New file.
	* gcc.target/aarch64/simd/vtrnu16_1.c: New file.
	* gcc.target/aarch64/simd/vtrnu16.x: New file.
	* gcc.target/aarch64/simd/vtrnu32_1.c: New file.
	* gcc.target/aarch64/simd/vtrnu32.x: New file.
	* gcc.target/aarch64/simd/vtrnu8_1.c: New file.
	* gcc.target/aarch64/simd/vtrnu8.x: New file.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210148 138bc75d-0d04-0410-961f-82ee72b054a4
2014-05-07  Richard Biener  <rguenther@suse.de>

	libcpp/
	* configure.ac: Always set need_64bit_hwint to yes.
	* configure: Regenerated.

	* config.gcc: Always set need_64bit_hwint to yes.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210149 138bc75d-0d04-0410-961f-82ee72b054a4
Really delete gcc/loop-unswitch.c.

	gcc/
	* loop-unswitch.c: Delete.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210150 138bc75d-0d04-0410-961f-82ee72b054a4
Reimplement AArch64 TRN intrinsics with __builtin_shuffle.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/vtrns32.c: Expect zip[12] insn rather than trn[12].
	* gcc.target/aarch64/vtrnu32.c: Likewise.
	* gcc.target/aarch64/vtrnf32.c: Likewise.

gcc/ChangeLog:

	* config/aarch64/arm_neon.h (vtrn1_f32, vtrn1_p8, vtrn1_p16, vtrn1_s8,
	vtrn1_s16, vtrn1_s32, vtrn1_u8, vtrn1_u16, vtrn1_u32, vtrn1q_f32,
	vtrn1q_f64, vtrn1q_p8, vtrn1q_p16, vtrn1q_s8, vtrn1q_s16, vtrn1q_s32,
	vtrn1q_s64, vtrn1q_u8, vtrn1q_u16, vtrn1q_u32, vtrn1q_u64, vtrn2_f32,
	vtrn2_p8, vtrn2_p16, vtrn2_s8, vtrn2_s16, vtrn2_s32, vtrn2_u8,
	vtrn2_u16, vtrn2_u32, vtrn2q_f32, vtrn2q_f64, vtrn2q_p8, vtrn2q_p16,
	vtrn2q_s8, vtrn2q_s16, vtrn2q_s32, vtrn2q_s64, vtrn2q_u8, vtrn2q_u16,
	vtrn2q_u32, vtrn2q_u64): Replace temporary asm with __builtin_shuffle.




git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210151 138bc75d-0d04-0410-961f-82ee72b054a4
[Patch, microblaze]: Add optimized lshrsi3

When barrel shifter is not present, the immediate value
is greater than #5 and optimization is -OS, the
compiler will generate shift operation using loop.

Changelog

2013-11-26  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn

ChangeLog/testsuite

2014-02-12  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test.

Signed-off-by:Nagaraju <nmekala@xilix.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Add INIT_PRIORITY support

Added TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros.

These macros allows users to control the order of initialization
of objects defined at namespace scope with the init_priority
attribute by specifying a relative priority, a constant integral
expression currently bounded between 101 and 65535 inclusive.

Lower numbers indicate a higher priority.

Changelog

2013-11-26  Nagaraju Mekala <nagaraju.mekala@xilinx.com>

 * gcc/config/microblaze/microblaze.c: Add microblaze_asm_constructor,
   microblaze_asm_destructor. Define TARGET_ASM_CONSTRUCTOR and
   TARGET_ASM_DESTRUCTOR.

Signed-off-by:nagaraju <nmekala@xilix.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Add supervisory call support

A function can be executed in supervisory mode when a function
is declared with svc_handler attribute.

If a function with svc_handler is called, the processor switches
to supervisory mode and executes. After executing the function
it returns to normal mode.

Same feature can also be invoked with svc_table_handler attribute
but this attribute will accept a service ID, to be used for
calling the function.

Signed-off-by:nagaraju <nmekala@xilix.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Added Break handler support

Break handler is used to support a normal hardware break.
This is similar to interrupt_handler except that RTBD should be used instead of RTID.

Signed-off-by:Nagaraju <nmekala@xilix.com>
Signed-off-by:David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Increase max alignment to please the testsuite

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
[Patch, microblaze]: Disable fivopts by default

Turn off ivopts by default. Interferes with cse.

Changelog

2013-03-18  Edgar E. Iglesias <edgar.iglesias@xilinx.com>

 * gcc/common/config/microblaze/microblaze-common.c
   (microblaze_option_optimization_table): Disable fivopts by default.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Use bralid for profiler calls

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
[Patch, microblaze]: Enable DWARF exception handling support.

Changelog

2013-03-18  Edgar E. Iglesias <edgar.iglesias@xilinx.com>
            David Holsgrove <david.holsgrove@xilinx.com>

 * common/config/microblaze/microblaze-common.c: Remove
   TARGET_EXCEPT_UNWIND_INFO definition.
 * config/microblaze/microblaze-protos.h: Add
   microblaze_eh_return prototype.
 * gcc/config/microblaze/microblaze.c: (microblaze_must_save_register,
   microblaze_expand_epilogue, microblaze_return_addr): Handle
   calls_eh_return
   (microblaze_eh_return): New function.
 * gcc/config/microblaze/microblaze.h: Define RETURN_ADDR_OFFSET,
   EH_RETURN_DATA_REGNO, MB_EH_STACKADJ_REGNUM, EH_RETURN_STACKADJ_RTX,
   ASM_PREFERRED_EH_DATA_FORMAT
 * gcc/config/microblaze/microblaze.md: Define eh_return pattern.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
[Patch, microblaze]: Fixed missing save of r18 in fast_interrupt.

Register 18 is used as a clobber register, and must be stored when
entering a fast_interrupt. Before this fix, register 18 was only
saved if it was used directly in the interrupt function.

However, if the fast_interrupt function called a function that used
r18, the register would not be saved, and thus be mangled
upon returning from the interrupt.

Changelog

2014-02-27  Klaus Petersen <klauspetersen@gmail.com>

 * gcc/config/microblaze/microblaze.c: Check for fast_interrupt in
   microblaze_must_save_register.

Signed-off-by: Klaus Petersen <klauspetersen@gmail.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, testsuite]: Add MicroBlaze to check_profiling_available

Testsuite, add microblaze*-*-* target in check_profiling_available
inline with other archs setting profiling_available_saved to 0

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, testsuite]: Add MicroBlaze pattern for dg-function-on-line

Add MicroBlaze specific pattern for checking line number and
generation of funtion in dg-function-on-line, in line with
mips method.

Changelog/testsuite

2014-02-13  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/testsuite/lib/scanasm.exp (dg-function-on-line): Add
   MicroBlaze specific pattern.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, testsuite]: Allow MicroBlaze .weakext pattern in regex match

Extend regex pattern to include optional ext at the end of
.weak to match the MicroBlaze weak label .weakext

ChangeLog/testsuite

2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/testsuite/g++.dg/abi/rtti3.C: Extend scan-assembler
   pattern to take optional ext after .weak.
 * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, testsuite]: Update MicroBlaze strings test

for new scan-assembly output resulting in use of $LC label

ChangeLog/testsuite

2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update
   to include $LC label.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, testsuite]: Add MicroBlaze to target-supports for atomic builtin tests

MicroBlaze added to supported targets for atomic builtin tests.

Changelog/testsuite

2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/testsuite/lib/target-supports.exp: Add microblaze to
   check_effective_target_sync_int_long.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[LOCAL]: For dejagnu static testing on qemu, suppress warnings

about multiple definitions from the test function and libc in line
with method used by powerpc. Dynamic linking and using a qemu binary
which understands sysroot resolves all test failures with builtins

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[LOCAL]: Testsuite - explicitly add -fivopts for tests that depend on it

(test gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt.c doesnt exist in 4.6 branch)

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>