Re: [AArch64] Fix possible wrong code generation when comparing DImode values.

gcc/

	* config/aarch64/aarch64-simd.md
	(aarch64_cm<optab>di): Always split.
	(*aarch64_cm<optab>di): New.
	(aarch64_cmtstdi): Always split.
	(*aarch64_cmtstdi): New.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@209617 138bc75d-0d04-0410-961f-82ee72b054a4
[AArch64] Add a space to memory asm code between base register and offset.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@209618 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/ChangeLog:

2014-04-22  Vidya Praveen  <vidyapraveen@arm.com>

	* aarch64.md (float<GPI:mode><GPF:mode>2): Remove.
	(floatuns<GPI:mode><GPF:mode>2): Remove.
	(<optab><fcvt_target><GPF:mode>2): New pattern for equal width float
	and floatuns conversions.
	(<optab><fcvt_iesize><GPF:mode>2): New pattern for inequal width float
	and floatuns conversions.
	* iterators.md (fcvt_target, FCVT_TARGET): Support SF and DF modes.
	(w1,w2): New mode attributes for inequal width conversions.

gcc/testsuite/ChangeLog:

2014-04-22  Vidya Praveen  <vidyapraveen@arm.com>

	* gcc.target/aarch64/vect_cvtf_1.c: New.



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@209620 138bc75d-0d04-0410-961f-82ee72b054a4