spi: tegra: cleanup in runtime_pm implementation.

Cleaning up runtime pm implementation for the driver.
There is lots of duplicate code which is not require as
it is handled in the runtime framework.

Change-Id: I4494cdd3518cbcb90f24fb3387f38c9859b4f957
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/102206
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
spi: tegra: synchronize PPSB late write

When any write is made to PPSB register, it take time
to actual happen in the register due to ARM-PPSB design.
Delay or readback is required to make sure that write is
completed. There is no worst case guaranteed delay and hence
doing the register read to make write completes actually.

Change-Id: Iefd25115e1a9f02c64e83f11a4e249ad9d086d16
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/102207
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
asoc: tegra: P1852 machine: Add TDM mode settings

Pass TDM mode variables for CPU dai.
Codec Id is not passed properly, hence use dual instances
of the dai_link operations.

Bug 948478

Change-Id: I13188d5001b8f9c2f2f67ee7a9d3bec89311037d
Signed-off-by: Bob Johnston <bjohnston@nvidia.com>
Reviewed-on: http://git-master/r/103793
Reviewed-by: Nitin Pai <npai@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>
video: tegra: detect fbmem alignment on probe

Detect the stride size used by the bootloader.
If DC is not enabled, fallback to a default stride size.

Bug 973111

Change-Id: If04647ddf04a44987cd841062ff30e03fa4d6a02
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/104031
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
net: wireless: bcm4329: Fix GCC 4.6 warning

This module has -Werror turned on, so this was causing the build to
break on GCC 4.6:

drivers/net/wireless/bcm4329/wl_iw.c: In function 'wl_iw_set_pmksa':
drivers/net/wireless/bcm4329/wl_iw.c:5149:5: error: array subscript is above array bounds [-Werror=array-bounds]
drivers/net/wireless/bcm4329/wl_iw.c:5152:5: error: array subscript is above array bounds [-Werror=array-bounds]

It's a partial 'backport' of a change made to the bcmdhd driver:

commit 09a8dc7361d0e603d9935ec7f736fabaa2e6dc7a
net: wireless: bcmdhd: Combined P2P fix

Change-Id: Ie62ad82f884c213553772ac91eaf85e17a807503
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/88694
GVS: Gerrit_Virtual_Submit
Reviewed-by: Stephen Warren <swarren@nvidia.com>
nvmap: Use linux conventions.

Avoid multiple CONFIG_TEGRA_NVMAP ifdefs.

Change-Id: Ic186a8203d8b2291d3d39ce8b612b33bee16f531
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/103937
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
mfd: tps80031: turn on backup battery charger circuit

The backup battery for the RTC circuit needs to be manually turned
on.  This change turns it on when the driver is first probed, off
during LP0 to prevent excess power draw, and back on again upon
resume.

Bug 986402

Change-Id: Id4768929d6a73546662806f04d98d714997174b0
Signed-off-by: Tom Cherry <tcherry@nvidia.com>
Reviewed-on: http://git-master/r/103425
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
asoc: tegra: utils: fix for multiple instances of extern1 clock.

The extern1 codec clock was not getting switched off whenever
codec goes below BIAS_OFF level. Moreover, there were two
instances of extern1 clock whenever codec was on. Reason behind
this was that, those codecs for which probe function was called
and were not present on board, turned on their extern1 clock, but
clean up routine (for switch device register failure) was not able
to turn off the clock. With this change, a conditional check is
put to turn off the clock.

(Bug 984678)
Signed-off-by: Ankit Gupta <ankitgupta@nvidia.com>

Change-Id: I585ecf73c0cabca856592dcd84e67588dfe13beb
Reviewed-on: http://git-master/r/104073
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Ankit Gupta (Engrg-SW) <ankitgupta@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
usb: gadget: android: add the handler for ptp class requests

Adding the handler for control requests of ptp
function driver.

Bug 980195

Change-Id: I3ddfc44d7ec4a98d29c7358be1f1d34799f92be9
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/103007
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
media: video: tegra: Add ad5816 focuser driver

- Implement new focuser ad5816 driver.
- Complies to latest NVC framework.

Bug 947792

Change-Id: I1661de027062d2a9b4112fd24dc255d810c7afa0
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/103131
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
CHROMEOS: add chrome kernel infrastructure

The ChromeOS build environment expects to build the kernel using a splitconfig.
This change adds the scripts and configs required to satisfy this requirement.
Right now the chromeos-tegra3 config is the only supported configuration using
the splitconfigs.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Change-Id: I21ac515261a03bdbe1c79bbd6cd02a6e34c82ef9
Reviewed-on: http://git-master/r/103683
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>
video: tegra: nvmap: Change function declaration order.

Change function declaration order to avoid multiple
CONFIG_TEGRA_NVMAP #ifdef's.

Change-Id: Icb10380f8da4b8037b90e787f961a28e8528814f
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/103990
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
video: tegra: nvmap: Clean up carveout to iovmm conversion.

Clean up carveout to iovmm conversion code.
Fixed bug in converting iovmm requests to carveout.

Change-Id: I35a5238c955d0478f0e1a295e501bae9ee52b0a8
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/103991
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
video: tegra: nvmap: Fix debug allocations data shown.

Debug allocations data for iovmm has carvout allocations
also and vice versa. Fixed it to show only iovmm for iovmm
and carveout for carveout.
Add missing "FLAGS" print for iovmm allocations.

Change-Id: I0fd271be24d0d2d3924ca473fd32476776fdcf84
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/104246
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
arm: tegra: ahci/sata: Add SATA driver

Upgrade the Tegra 3 SATA driver to support kernel 3.1.

The driver supports runtime_pm when doing power-gating during idle.

A new CONFIG_TEGRA_SATA_IDLE_POWERGATE is provided to enable/disable
power-gating during idle.

When sata clocks (sata, sata-oob and pll_e clocks) are in the
core_dvfs_table[] table, CONFIG_TEGRA_SATA_IDLE_POWERGATE must not
be enabled.

Currently, sata clocks are in the core_dvfs_table[]. Those clocks
will not be in that table in the future. By then,
CONFIG_TEGRA_SATA_IDLE_POWERGATE can then be enabled.

Change-Id: I15b585713bfd891f8827fd028b21bf3e5c2b80d9
Signed-off-by: Yen Lin <yelin@nvidia.com>
Reviewed-on: http://git-master/r/89614
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Revert "video: tegra: host: t30: use max 2d clock"

This reverts commit 5bdd03b21f625d0a07c66e4894b79e557287a3a1.

The reverted commit kept vcore at 1.2 volts whenever 2D engine is on
and increased power consumption for use cases that utilize 2D but
doesn't require its full speed.

Bug 979545

Change-Id: I4297ab1fb83558501ff620952284c8590dc5f1dd
Signed-off-by: Wen Yi <wyi@nvidia.com>
Reviewed-on: http://git-master/r/104293
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Donghan Ryu <dryu@nvidia.com>
Tested-by: Donghan Ryu <dryu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Revert "Revert "arm: tegra3: change min_rate for clocks""

This reverts commit 18ed77b122dd1fbb9a6a5373da36ab32d0f0cee1.
The noisy audio playback on Tegra3 with secure-OS issue is fixed by
updating TL's SDK to 1.08. Change min_rate for clocks back to 12Mhz.

Bug 939415

Change-Id: Ib0daf98faa85cc7cbc1dbfd4bf458427f914d830
Signed-off-by: Hunk Lin <hulin@nvidia.com>
Reviewed-on: http://git-master/r/104317
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Arm: Tegra3: clocks: Disabled SSCCENTER bit for plle

Disabled SSCCENTRE bit for plle as per golden register
(value provided by syseng)

Bug 942384 978870

Change-Id: I3c2f8e8e220015b58f0c8bcbaac4e9998a5b6dcd
Reviewed-on: http://git-master/r/98381
Signed-off-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-on: http://git-master/r/102408
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
arm: tegra: kai: configure gpio direction for bluesleep

Bug 986813

Change-Id: Iaca0465041af3442da8e052e3efec1efa60d0d79
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: http://git-master/r/103632
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ASoC: resolve compilation time warnings

Bug 949219

Change-Id: If7b4dd928cc5a808fd1a674bcc5f31c9a396a043
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/103772
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>