Run on FPGA
Modify alutb.vhd
Create bsadd8-p (bit-slice adder with pipeline)
Assignment 5 (simulation ok)
[Error] Bytes that were sent are doubled (x -> x<<1)
[Fix] 1adb->1c07

improve test bench
modify input (week 5)
W5-optional
Improve Calculation
Add .gitignore to hw7
Rewrite Makefile
Fix errors in fadd.c
Add test cases
Fix bugs in fadd.c
Write fadd32.vhd
Fix fadd.c
Fix fadd32
Write test bench

Test bench can read file in.txt
Add test generator
Write test cases

On simulator fadd32 passes all test cases