Target: whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206353 91177308-0d34-0410-b5e6-96231b3b80d8
tools: fix invalid printing, buffer overrun in llvm-readobj

All auxiliary records are consumed when accessing a File record.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206354 91177308-0d34-0410-b5e6-96231b3b80d8
COFF: add support for .file symbols

Add support for emitting .file records.  This is mostly a quality of
implementation change (more complete support for COFF file emission) that was
noticed while working on COFF file emission for Windows on ARM.

A .file record is emitted as a symbol with storage class FILE (103) and the name
".file".  A series of auxiliary format 4 records follow which contain the file
name.  The filename is stored as an ANSI string and is padded with NULL if the
length is not a multiple of COFF::SymbolSize (18).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206355 91177308-0d34-0410-b5e6-96231b3b80d8
[C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206356 91177308-0d34-0410-b5e6-96231b3b80d8
Convert SelectionDAG::getVTList to use ArrayRef

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206357 91177308-0d34-0410-b5e6-96231b3b80d8
COFF: fix an off by one error

Adjust the tests to validate the number of auxiliary entries used to store the
filename.

Thanks to majnemer's sharp eye for catching the missing - 1 in the round up
calculation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206359 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify a static_assert so VS2013 can build it

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206363 91177308-0d34-0410-b5e6-96231b3b80d8
DAGCombiner: don't optimise non-existant litpool load

This particular DAG combine is designed to kick in when both ConstantFPs will
end up being loaded via a litpool, however those nodes have a semi-legal
status, dictated by isFPImmLegal so in some cases there wouldn't have been a
litpool in the first place. Don't try to be clever in those circumstances.

Picked up while merging some AArch64 tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206365 91177308-0d34-0410-b5e6-96231b3b80d8
ARM64: mark x7 as used when an i128 gets shunted onto the stack.

The second half of a split i128 was ending up in x7, which is not a good thing.

This is another part of PR19432.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206366 91177308-0d34-0410-b5e6-96231b3b80d8
ARM64: explicitly ask for Apple NEON syntax so test passes on Linux

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206368 91177308-0d34-0410-b5e6-96231b3b80d8
[Allocator] Nuke to useless functions. The implicit ones are sufficient
here (obviously).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206369 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Add calling convention tests covering O32, N32, and N64.

Summary:
I had difficulty finding tests for the N32 and N64 ABI so I've added a
collection of calling convention tests based on the document MIPS ABIs
Described (MD00305), the MIPSpro N32 Handbook, and the SYSV ABI. Where the
documents/implementations disagree, I've used GCC to resolve the conflict.

A few interesting details:
* For N32, LLVM uses 64-bit pointers when saving $ra despite pointers being
  32-bit. I've yet to find a supporting statement in the ABI documentation but
  the current behaviour matches GCC.

* For O32, the non-variable portion of a varargs argument list is also subject
  to the rule that floating-point is passed via GPR's (on N32/N64 only the
  variable portion is subject to this rule). This agrees with GCC's behaviour
  and the SYSV ABI but contradicts part of the MIPSpro N32 Handbook which talks about O32's behaviour.

* The N32 implementation has the wrong callee-saved register list.
  (I already have a fix for this but will commit it as a follow-up).

I've left RUN-TODO lines in for O32 on MIPS64. I don't plan to support this case
for now but we should revisit it.

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3339

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206370 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Correct callee saved list for the N32 ABI and enable test

Summary: Depends on D3339

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3340

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206371 91177308-0d34-0410-b5e6-96231b3b80d8
[Allocator] Make BumpPtrAllocator movable and move assignable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206372 91177308-0d34-0410-b5e6-96231b3b80d8
[LCG] Stop playing fast and loose with reference members and assignment.
It doesn't work. I'm still cleaning up all the places where I blindly
followed this pattern. There are more to come in this code too.

As a benefit, this lets the default copy and move operations Just Work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206375 91177308-0d34-0410-b5e6-96231b3b80d8
Fixing a compile error in debug versions of MSVC. It seems that the range-based for loop is confused by the DEBUG macro expansion unless a compound statement is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206376 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Emit '.set nomicromips' before a function's entry label
if not in micromips mode.

The test (elf_st_other.ll) was renamed as the name and description didn't
make sense as the test wasn't checking any symbol table entry.

Differential Revision: http://reviews.llvm.org/D3346



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206377 91177308-0d34-0410-b5e6-96231b3b80d8
ARM64: use the integrated assembler on ELF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206378 91177308-0d34-0410-b5e6-96231b3b80d8
ARM64: use 32-bit moves for constants where possible.

If we know that a particular 64-bit constant has all high bits zero, then we
can rely on the fact that 32-bit ARM64 instructions automatically zero out the
high bits of an x-register. This gives the expansion logic less constraints to
satisfy and so sometimes allows it to pick better sequences.

Came up while porting test/CodeGen/AArch64/movw-consts.ll: this will allow a
32-bit MOVN to be used in @test8 soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206379 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64/ARM64: port across stub handling for ELF C++ exceptions.

The most important part here is that we should actuall emit the stubs we refer
to in the exception table, but as a side issue this uses more sensible & GCC
compatible representations for some of the bits of information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206380 91177308-0d34-0410-b5e6-96231b3b80d8