Add beamformer (phased sum) functionality

This adds the beamformer (aka phased summer) functionality to the `sma_corr`
model.  All of the change is contained within the new `beng` (Beamformer
ENGine) block at the top level.

Summary of new devices:

  * `beng/gain` (R/W register) Low 8 bits are UFix_8_4 gain factor applied to
    the summed data.  The summed data values are Fix_8_0, but the MSb is
    redundant (they are really only Fix_7_0).  The data values are reinterpretd
    as Fix_8_3 and then multiplied by the UFix_8_4 gain factor which gives
    Fix_16_7.  The Fix_16_7 value is cast to a Fix_4_0 with saturation and
    round-to-even.

  * `beng/eth/core` (10 GbEv2 core) Transmits phased sum data over SFP+ port 1
    on mezzanaine slot 0.  Port 48803 is used for beamformer UDP packets.
    48803 is 0xbea3, which spells "beam" with a rotated "m". :-)

  * `beng/eth/ctrl` (R/W register) Bit 31 (MSb) is the enable bit for phased
    sum data transmission.  Bit 30 is resets the Ethernet core and the TX
    overflow status counter.

  * `beng/eth/dest_ip` (R/W register) 32 bit destination IP to which phases sum
    data packets are sent.  All packets from a given ROACH2 are sent to this
    one IP address.

  * `beng/eth/status` (R/O register) Bit 31 (MSb) is the instantaneous TX
    almost full status bit.  Bit 30 is the instantaneous TX overflow bit.  Bits
    29:0 are a 30-bit count of TX overflow cycles.  All bits should always read
    zero.  This register is reset by bit 30 of `beng/eth/ctrl`.