x86: Fixes PCI 8 and 16 byte accesses

Instead of reading and writing on 32 byte boundaries, you are supposed
to access on the 32 byte boundary, but then do the data read/write from
an offsetted *IO port*.  There are a few of them, which sort of read
from the space directly.  Ugh.

Also, the offset into the config space will need to be up to 4KB, not
256, for PCI-E.  Ugh.
PCI: properly read the BARs

Was not stripping the MF bit, so multi-func BARs were coming back 0.
igbe: abort MSI for a shitty NIC

Not sure if it is HW or us, but MSI works on two other NICs.  On the
82545EM, once we use MSI, the NIC clobbers the RD buffer area with
gibberish.
Increase max nr NICs

c89 has more than 4.  But who could ever need more than 32?!?