The following commits: register synthesis and deprecated VHDL cleanup.

The initial values assigned to the signals and the reset values
were not the same.  This resulted in the synthesis tool to incorrectly
identify (possibly) the register - or at least the reset value.
The Xilinx XST tool produced a Warning:3002 "This design contains
registers/latches are are incompatible with the Spartan6 architecture
... has an init value of opposite polartiy as reset".

The other modification was to remove the non-standardized use of the
std_logic_arith and std_logic_unsigned.  The DCT code was modified to
use the standarized numeric_std.  This required changing some of the
conversion functions available in numeric_std.  More information
on why not to use std_logic_arith and std_logic_unsigned is available
here: http://www.sigasi.com/content/deprecated-ieee-libraries