test/SyncFIFOCase: better test bench termination
mibuild/altera_quartus: add support for verilog include
mibuild/altera_quartus: set top_level_entity
mibuild: add bitstream_ext parameter to platforms
genlib/fifo: add SyncFIFORelaxed

In some instances XST fails to map SyncFIFO to BRAM because of the
asynchronous read. This adds a FWFT FIFO that always registers dout and
should be mappable to BRAM in all cases. It also adds a bypass around
the entire thing to achieve the same behavior and latency as SyncFIFO.