Add a method to get the PCI RID for a device.

Reviewed by:	kib
MFC after:	2 months
Sponsored by:	Sandvine Inc.
Re-implement the DMAR I/O MMU code in terms of PCI RIDs

Under the hood the VT-d spec is really implemented in terms of
PCI RIDs instead of bus/slot/function, even though the spec makes
pains to convert back to bus/slot/function in examples.  However
working with bus/slot/function is not correct when PCI ARI is
in use, so convert to using RIDs in most cases.  bus/slot/function
will only be used when reporting errors to a user.

Reviewed by:	kib
MFC after:	2 months
Sponsored by:	Sandvine Inc.
Re-write bhyve's I/O MMU handling in terms of PCI RID.

Reviewed by:	neel
MFC after:	2 months
Sponsored by:	Sandvine Inc.
Support serial speeds up to 12mbaud with newer FTDI chips.

Recent FDTI chips have the ability to operate at up to 12mbps.  The newer
chips with faster clocks have the same usb vendor/product IDs as the older
chips; the bcdDevice field must be used to detect the newer versions.  This
change includes a new function to do that instead of using just the IDs from
the vendor/product table.

The code to choose the baud clock divisor is completely rewritten.  In
addition to supporting the new higher clock rates, the rewrite fixes a
longstanding bug in the old code which put the high bits of the fractional
part of the divisor into the wrong place in the wIndex field.  That bug
was mostly harmless -- it accidentally didn't affect standard baud rates
and would only show up when using relatively fast non-standard rates.
Add support for PCIe ARI

PCIe Alternate RID Interpretation (ARI) is an optional feature that
allows devices to have up to 256 different functions.  It is
implemented by always setting the PCI slot number to 0 and
re-purposing the 5 bits used to encode the slot number to instead
contain the function number.  Combined with the original 3 bits
allocated for the function number, this allows for 256 functions.

This is enabled by default, but it's expected to be a no-op on currently
supported hardware.  It's a prerequisite for supporting PCI SR-IOV, and
I want the ARI support to go in early to help shake out any bugs in it.
ARI can be disabled by setting the tunable hw.pci.enable_ari=0.

Reviewed by:	kib
MFC after:	2 months
Sponsored by:	Sandvine Inc.
Print status of ARI capability in pciconf -c

Teach pciconf how to print out the status (enabled/disabled) of the ARI
capability on PCI Root Complexes and Downstream Ports.

MFC after:	2 months
Sponsored by:	Sandvine Inc.