APPLIED: ARM: tegra: add Jetson TK1 device tree

Jetson TK1 is an NVIDIA Tegra124 development board, containing Tegra124,
2GB RAM, eMMC, SD card, SPI flash, serial port, PCIe Ethernet, HDMI,
audio, mini PCIe, JTAG, SATA, and an expansion IO connector containing
GPIOs, I2C, SPI, CSI, eDP, etc.

The following features work with this device tree: UART, SD card, eMMC,
SPI flash, USB (full-size jack, and mini-PCIe), audio, AS3722 RTC, system
power-off, suspend/resume (LP1) with wake via RTC alarm.

The following features should work with this device tree, but are not
validated: Expansion I2C, expansion SPI, expansion GPIO, gpio-key for the
power button.

The following features are not yet implemented in this device tree: Most
voltage regulators, expansion UART, HDMI, eDP, PCIe (Ethernet, and mini-
PCIe connector), CSI, SATA.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
APPLIED: ARM: tegra: enable AT24C EEPROM driver

This is used for the board ID EEPROM on Jetson TK1, as well as likely
a whole slew of other NVIDIA reference boards; we simply haven't added
enabled the EEPROM in the DT files until now.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
APPLIED: ARM: tegra: define Jetson TK1 regulators

These are mostly identical to the Venice2 regulator definitions, since
the board designs are very similar. Differences are:

- Jetson TK1 doesn't have a built-in LCD panel, so on-board regulators
  are not present for the backlight, touchscreen, or panel.
- +3.3V_RUN needs to be boot-on/always-on, since it's widely used. This
  change should likely be propagated to Venice2 for completeness,
  although it will have no practical effect there since various other
  regulators use +3.3V_RUN as their supply and are always-on.
- +3.3V_LP0 needs to be boot-on as well as always-on. One reason
  is because it's used to driver the UART level-shifter; without this, I
  see a brief period of UART corruption during cold boots.I suspect this
  change needs to be propagated to Venice2, and we simply haven't noticed
  the need since there's no UART level-shifter on Venice2.
- A few rails have different names in the schematics.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: remove UART5/UARTE from tegra124.dtsi

Tegra124 only has 4 UARTs. Parts of the documentation hint at a fifth
UART, but this appears to be left-over from earlier SoC documentation.
Remove the non-existent DT node for UART5.

Cc: <stable@vger.kernel.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
clk: tegra: remove non-existent clocks

The Tegra124 clock driver currently provides 3 clocks that don't actually
exist; 2 for NAND and one for UART5/UARTE. Delete these.

Cc: <stable@vger.kernel.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
dt: tegra: remove non-existent clock IDs

The Tegra124 clock DT binding currently provides 3 clocks that don't
actually exist; 2 for NAND and one for UART5/UARTE. Delete these. While
this is technically an incompatible DT ABI change, nothing could have
used these clock IDs for anything practical, since the HW doesn't exist.

Cc: <stable@vger.kernel.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This depends on the previous 2 patches. Either all the patches can be
taken through the same tree with acks, or we can hold of applying this
patch until the other two make it into Linus' tree.
gpu: host1x: handle the correct # of syncpt regs

BIT_WORD() truncates rather than rounds, so the loops in
syncpt_thresh_isr() and _host1x_intr_disable_all_syncpt_intrs() use <=
rather than < in an attempt to process the correct number of registers
when rounding of the conversion of count of bits to count of words is
necessary. However, when rounding isn't necessary because the value is
already a multiple of the divisor (as is the case for all values of
nb_pts the code actually sees), this causes one too many registers to
be processed.

Solve this by using and explicit DIV_ROUND_UP() call, rather than
BIT_WORD(), and comparing with < rather than <=.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
v2: Use DIV_ROUND_UP rather than BITS_TO_LONGS to avoid problems on 64-bit.
ARM: tegra: remove TEGRA_EMC_SCALING_ENABLE

Commit a7cbe92cef27 ("ARM: tegra: remove tegra EMC scaling driver")
removed the only user of TEGRA_EMC_SCALING_ENABLE. Remove its Kconfig
entry too.

Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
USB: EHCI: tegra: set txfill_tuning

To avoid memory fetch underflows with larger USB transfers, Tegra SoCs
need txfill_tuning's txfifothresh register field set to a non-default
value. Add a custom reset override in order to set this up.

These values are recommended practice for all Tegra chips. However,
I've only noticed practical problems when not setting them this way on
systems using Tegra124. Hence, CC: stable only for recent kernels which
actually support Tegra124.

Cc: <stable@vger.kernel.org> # 3.14+
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
pinctrl: tegra: remove redundant data table fields

Any SoC which supports the einput, odrain, lock, ioreset, or rcv_sel
options has the relevant HW register fields in the same register as the
mux function selection. Similarly, the drvtype option is always in the
drive register, if it is supported at all. Hence, we don't need to have
struct *_reg fields in the pin group table to define which register and
bank to use for those options. Delete this to save space in the driver's
data tables.

However, many of those options are not supported on all SoCs, or not
supported on some pingroups. We need a way to detect when they are
supported. Previously, this was indicated by setting the struct *_reg
field to -1. With the struct *_reg fields removed, we use the struct
*_bit fields for this purpose instead. The struct *_bit fields need to
be expanded from 5 to 6 bits in order to store a value outside the valid
HW bit range of 0..31.

Even without removing the struct *_reg fields, we still need to add code
to validate the struct *_bit fields, since some struct *_bit fields were
already being set to -1, without an option-specific struct *_reg field to
"guard" them. In other words, before this change, the pinmux driver might
allow some unsupported options to be written to HW.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
(Note: For V2, I'm only reposting patch 1/4, since patch 2/4 is large, and
I don't want to spam the list again with the whole series)

v2:
* Modify width of struct tegra_pingroup's drvtype_bit in the same way as
  other *_bit fields.
* Fix struct tegra_pingroup's documentation to match the changes made
  to the struct.
* Fix pinctrl-tegra20.c's DRV_PG_EXT() macro to initialize the drvtype_bit
  field.
pinctrl: tegra: remove fsafe from data tables

The fsafe value in the pingroup data tables is only used to implement
tegra_pinctrl_disable(). The only reason this function is called is when
dynamically switching between pinmux states, i.e. when disabling the old
state before programming the new state. It's simpler to have the new
target state define the expected value of each pin (and all current DTs
do that). This also gives more flexibility, since it allows individual
boards explicit control over the "inactive" mux function for each pin,
rather than requiring it to be an SoC-specific value. Assuming this, we
can get rid of the fsafe value from the driver completely, thus saving
some more space in the driver tables.

While re-writing the content of tegra124_pingroups[], fix the indentation
to use a TAB instead of spaces.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
pinctrl: tegra: reduce size of data table fields

The range of npins and function ID values is small enough to fit into a
u8. Use this type rather than unsigned to shrink the pinmux data tables.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
pinctrl: tegra: print better error messages

When an attempt is made to configure an unsupported option on a pin,
print the DT property name of that option, so it's easier to debug
what the problem is.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
pinctrl: tegra: add missing kerneldoc

The kerneldoc for struct tegra_pingroup didn't describe all of the fields
in the struct. Add some extra kerneldoc to fix that.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
mmc: tegra: disable UHS modes

Program TEGRA_SDHCI_VENDOR_MISC_CTRL so that UHS modes aren't advertised
in SDHCI_CAPABILITIES_1.  While the Tegra SDHCI controller does support
these modes, they require Tegra-specific tuning and calibration routines
which the driver does not support yet.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
mmc: tegra: fix reporting of base clock frequency

Tegra SDHCI controllers, by default, report a base clock frequency
of 208Mhz in SDHCI_CAPABILTIES which may or may not be equal to the
actual base clock frequency.  While this can be overridden by setting
BASE_CLK_FREQ in VENDOR_CLOCK_CTRL on Tegra30 and later SoCs, just
set SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN and supply a get_max_clock()
callback to get the actual rate of the base clock.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: fix Venice2 VQMMC regulators

VDDIO_SDMMC3 is the VQMMC supply, not the VMMC supply, for the SD
slot.  Add 1.8V_VDDIO as the VQMMC supply for the eMMC.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: rebuild tegra_defconfig on next-20140319

Signed-off-by: Stephen Warren <swarren@nvidia.com>
LOCAL HACK: tegra_defconfig changes

Signed-off-by: Stephen Warren <swarren@nvidia.com>
ARM: tegra: bluetooth testing hacks for Cardhu

Signed-off-by: Stephen Warren <swarren@nvidia.com>