Removed signals from entity of std_sig.vhd & TBstd_sig.vhd
	  --sigDel_s : in STD_LOGIC;
	  --sigDelayed_s : out STD_LOGIC;
 	  --left_sv : in  STD_LOGIC_VECTOR :=(15 downto 0 => '0');
          -- leftDelDut_s : out  STD_LOGIC_VECTOR :=(15 downto 0 => '0');
--  These are now in ARCHITECTURE before  the begin
	  signal sigDel_s :  STD_LOGIC;
	  signal sigDelayed_s :  STD_LOGIC;
 	  signal left_sv : STD_LOGIC_VECTOR (15 downto 0);
          signal leftDelDut_s : STD_LOGIC_VECTOR (15 downto 0);
--  These are now in ARCHITECTURE after  the begin
DelayBus_u0 : DelayBus
	generic map (NUM_DELAY_CYCLES_G => 2)
		port map (
		      --clk_s => clk_s,
			   --This clk used during simulation
				clk_i => clk_i,
				bus_i => left_sv,
				busDelayed_o => leftDelDut_s
				);

DelayLine_u1 : DelayLine
	generic map (NUM_DELAY_CYCLES_G => 2)
		port map (
		      --clk_s => clk_s,
			   --This clk used during simulation
				clk_i => clk_i,
				a_i => sigDel_s,
				aDelayed_o => sigDelayed_s
				);