add stuff to .gitignore
create rtt_probe
add copies of sources that will be modified
add synth/ to .gitignore
append 8 bytes to all packets sent
append timestamp to transmitted packets
add remapping of packets

using one-hot mapping remap packets coming from PHY3
to PHY0 and PHY1; output queues should replicate
add stuff created on coregen run to .gitignore

I needed coregen to create a custom fifo, it's files
are saved in local coregen/ directory, but there is no
need for them in repo.
add rx timestamping
add new fifo used in rx timestamping
.gitignore: add better granularity to files in synth/
reverse order of bytes in tx timestamps
initial commit preparing for gathering statistics
use internal clock for tx stamping as well

I should use the same clock from both timestamps.
Internal, main FPGA clock seems most reliable.
It's already used for RX stamping.
remove verilog files generated by coregen