msm: thermal: add my cleaned up in-kernel driver

 * mostly copy-pasta from the N5
 * thermal-engine daemon is disabled in userspace
 * users can now ajudst the thermal throttle point in sysfs
 * well... it's clean :)
 * stability test responds very well and the device doesn't
heat up too much. On stock thermal solution the device rapidly
reached un-bearable temperature on the back (running stability test)
due to it's weird throttling mechanics (at least from what we can
observe since the code is proprietary) and doesn't cool down easily.
With this solution that doesn't happen.

Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: kgsl: Use high priority workqueue

Change-Id: If245f7876a68da079b2e0b9e371fdcbeb85ef0b5
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
futex: Prevent attaching to kernel threads

We happily allow userspace to declare a random kernel thread to be the
owner of a user space PI futex.

Found while analysing the fallout of Dave Jones syscall fuzzer.

We also should validate the thread group for private futexes and find
some fast way to validate whether the "alleged" owner has RW access on
the file which backs the SHM, but that's a separate issue.

Change-Id: I4d06d7717f73e9cc6c2ef2a8c8b39b4cc35da072
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Dave Jones <davej@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Darren Hart <darren@dvhart.com>
Cc: Davidlohr Bueso <davidlohr@hp.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Clark Williams <williams@redhat.com>
Cc: Paul McKenney <paulmck@linux.vnet.ibm.com>
Cc: Lai Jiangshan <laijs@cn.fujitsu.com>
Cc: Roland McGrath <roland@hack.frob.com>
Cc: Carlos ODonell <carlos@redhat.com>
Cc: Jakub Jelinek <jakub@redhat.com>
Cc: Michael Kerrisk <mtk.manpages@gmail.com>
Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Link: http://lkml.kernel.org/r/20140512201701.194824402@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
Added fsync on/off support.

Change-Id: I0328e1a50ec102fa073dbaaea953fe3da7b53077
Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
fs: sync: enable fsync by default.

Change-Id: If41dd9ea11c88a702045372826eeb75dfdfb256e
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
fs: sync: add missing return if fsync is disabled from userspace.

Change-Id: Ic64eeb31645cc5367bd6a45e778369c7f523c9d6
Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
fsync: correct permissions, cleanup introduced whitespaces

Change-Id: I0203417e3bd36d559b86c800800a7f7dcd090e07
ARM: 7493/1: use generic unaligned.h

This moves ARM over to the asm-generic/unaligned.h header. This has the
benefit of better code generated especially for ARMv7 on gcc 4.7+
compilers.

As Arnd Bergmann, points out: The asm-generic version uses the "struct"
version for native-endian unaligned access and the "byteshift" version
for the opposite endianess. The current ARM version however uses the
"byteshift" implementation for both.

Thanks to Nicolas Pitre for the excellent analysis:

Test case:

int foo (int *x) { return get_unaligned(x); }
long long bar (long long *x) { return get_unaligned(x); }

With the current ARM version:

foo:
	ldrb	r3, [r0, #2]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 2B], MEM[(const u8 *)x_1(D) + 2B]
	ldrb	r1, [r0, #1]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 1B], MEM[(const u8 *)x_1(D) + 1B]
	ldrb	r2, [r0, #0]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D)], MEM[(const u8 *)x_1(D)]
	mov	r3, r3, asl #16	@ tmp154, MEM[(const u8 *)x_1(D) + 2B],
	ldrb	r0, [r0, #3]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 3B], MEM[(const u8 *)x_1(D) + 3B]
	orr	r3, r3, r1, asl #8	@, tmp155, tmp154, MEM[(const u8 *)x_1(D) + 1B],
	orr	r3, r3, r2	@ tmp157, tmp155, MEM[(const u8 *)x_1(D)]
	orr	r0, r3, r0, asl #24	@,, tmp157, MEM[(const u8 *)x_1(D) + 3B],
	bx	lr	@

bar:
	stmfd	sp!, {r4, r5, r6, r7}	@,
	mov	r2, #0	@ tmp184,
	ldrb	r5, [r0, #6]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 6B], MEM[(const u8 *)x_1(D) + 6B]
	ldrb	r4, [r0, #5]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 5B], MEM[(const u8 *)x_1(D) + 5B]
	ldrb	ip, [r0, #2]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 2B], MEM[(const u8 *)x_1(D) + 2B]
	ldrb	r1, [r0, #4]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 4B], MEM[(const u8 *)x_1(D) + 4B]
	mov	r5, r5, asl #16	@ tmp175, MEM[(const u8 *)x_1(D) + 6B],
	ldrb	r7, [r0, #1]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 1B], MEM[(const u8 *)x_1(D) + 1B]
	orr	r5, r5, r4, asl #8	@, tmp176, tmp175, MEM[(const u8 *)x_1(D) + 5B],
	ldrb	r6, [r0, #7]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 7B], MEM[(const u8 *)x_1(D) + 7B]
	orr	r5, r5, r1	@ tmp178, tmp176, MEM[(const u8 *)x_1(D) + 4B]
	ldrb	r4, [r0, #0]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D)], MEM[(const u8 *)x_1(D)]
	mov	ip, ip, asl #16	@ tmp188, MEM[(const u8 *)x_1(D) + 2B],
	ldrb	r1, [r0, #3]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 3B], MEM[(const u8 *)x_1(D) + 3B]
	orr	ip, ip, r7, asl #8	@, tmp189, tmp188, MEM[(const u8 *)x_1(D) + 1B],
	orr	r3, r5, r6, asl #24	@,, tmp178, MEM[(const u8 *)x_1(D) + 7B],
	orr	ip, ip, r4	@ tmp191, tmp189, MEM[(const u8 *)x_1(D)]
	orr	ip, ip, r1, asl #24	@, tmp194, tmp191, MEM[(const u8 *)x_1(D) + 3B],
	mov	r1, r3	@,
	orr	r0, r2, ip	@ tmp171, tmp184, tmp194
	ldmfd	sp!, {r4, r5, r6, r7}
	bx	lr

In both cases the code is slightly suboptimal.  One may wonder why
wasting r2 with the constant 0 in the second case for example.  And all
the mov's could be folded in subsequent orr's, etc.

Now with the asm-generic version:

foo:
	ldr	r0, [r0, #0]	@ unaligned	@,* x
	bx	lr	@

bar:
	mov	r3, r0	@ x, x
	ldr	r0, [r0, #0]	@ unaligned	@,* x
	ldr	r1, [r3, #4]	@ unaligned	@,
	bx	lr	@

This is way better of course, but only because this was compiled for
ARMv7. In this case the compiler knows that the hardware can do
unaligned word access.  This isn't that obvious for foo(), but if we
remove the get_unaligned() from bar as follows:

long long bar (long long *x) {return *x; }

then the resulting code is:

bar:
	ldmia	r0, {r0, r1}	@ x,,
	bx	lr	@

So this proves that the presumed aligned vs unaligned cases does have
influence on the instructions the compiler may use and that the above
unaligned code results are not just an accident.

Still... this isn't fully conclusive without at least looking at the
resulting assembly fron a pre ARMv6 compilation.  Let's see with an
ARMv5 target:

foo:
	ldrb	r3, [r0, #0]	@ zero_extendqisi2	@ tmp139,* x
	ldrb	r1, [r0, #1]	@ zero_extendqisi2	@ tmp140,
	ldrb	r2, [r0, #2]	@ zero_extendqisi2	@ tmp143,
	ldrb	r0, [r0, #3]	@ zero_extendqisi2	@ tmp146,
	orr	r3, r3, r1, asl #8	@, tmp142, tmp139, tmp140,
	orr	r3, r3, r2, asl #16	@, tmp145, tmp142, tmp143,
	orr	r0, r3, r0, asl #24	@,, tmp145, tmp146,
	bx	lr	@

bar:
	stmfd	sp!, {r4, r5, r6, r7}	@,
	ldrb	r2, [r0, #0]	@ zero_extendqisi2	@ tmp139,* x
	ldrb	r7, [r0, #1]	@ zero_extendqisi2	@ tmp140,
	ldrb	r3, [r0, #4]	@ zero_extendqisi2	@ tmp149,
	ldrb	r6, [r0, #5]	@ zero_extendqisi2	@ tmp150,
	ldrb	r5, [r0, #2]	@ zero_extendqisi2	@ tmp143,
	ldrb	r4, [r0, #6]	@ zero_extendqisi2	@ tmp153,
	ldrb	r1, [r0, #7]	@ zero_extendqisi2	@ tmp156,
	ldrb	ip, [r0, #3]	@ zero_extendqisi2	@ tmp146,
	orr	r2, r2, r7, asl #8	@, tmp142, tmp139, tmp140,
	orr	r3, r3, r6, asl #8	@, tmp152, tmp149, tmp150,
	orr	r2, r2, r5, asl #16	@, tmp145, tmp142, tmp143,
	orr	r3, r3, r4, asl #16	@, tmp155, tmp152, tmp153,
	orr	r0, r2, ip, asl #24	@,, tmp145, tmp146,
	orr	r1, r3, r1, asl #24	@,, tmp155, tmp156,
	ldmfd	sp!, {r4, r5, r6, r7}
	bx	lr

Compared to the initial results, this is really nicely optimized and I
couldn't do much better if I were to hand code it myself.

Change-Id: I91ea5a5e83de4bbdbb53883fe0dbf00719a8e382
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
lib/lzo: huge LZO decompression speedup on ARM by using unaligned access

Change-Id: I88eceb209b3739c2819779c14e5e46213f1f2fce
Signed-off-by: Markus F.X.J. Oberhumer <markus@oberhumer.com>
lzo: properly check for overruns

commit 206a81c18401c0cde6e579164f752c4b147324ce upstream.

The lzo decompressor can, if given some really crazy data, possibly
overrun some variable types.  Modify the checking logic to properly
detect overruns before they happen.

Change-Id: I3a4ad3d313ed0052b58fec5dfec01b1ac7730e21
Reported-by: "Don A. Bailey" <donb@securitymouse.com>
Tested-by: "Don A. Bailey" <donb@securitymouse.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
bacon/find7: Compress kernel with LZO instead of XZ

Change-Id: I20e842a34c864ad6420f032825268591dd0241ae
wlan: add check for size of cache aligned skb->data

In receive path we check if the memory DMA'd is more
than the allocated memory. alloc_skb() can allocate
more memory than specified if the specified memory
size is not cache aligned, so check for the size
of cache aligned memory for deciding if the data
DMA's was more that allocated memory.

Change-Id: Iaf5b75b73d1f84d6d64ed0975414218a7bb6f591
CRs-Fixed: 717798
net/ipv6/addrconf: fix wdog_bark caused by infinite spinning on a deadlock

A synchronization issue may occur while addrconf_ifdown(),
when it updates inet6_addr_lst[] with already destroyed *ifp
by ipv6_add/del_addr(), using the same addrconf_hash_lock.

[core 0]                                        [core 1]
   |                                               |
   |->ipv6_add_addr                                |->addrconf_ifdown
       |                                               |
       |                                               |-> spin_lock(&addrconf_hash_lock);
       |                                               |-> remove ifa->addr_lst from inet6_addr_lst
       |                                               |-> spin_unlock(&addrconf_hash_lock);
       |-> spin_lock(&addrconf_hash_lock);             |
       |-> add ifa->addr_lst to inet6_addr_lst[hash]   |
       |-> spin_unlock(&addrconf_hash_lock);           |
       |-> write_lock(&idev-lock);                     |
       |-> add ifa->if_list to idev->addr_list         |
       |-> write_unlock(&idev->lock);                  |
       |                                               |-> write_lock(&idev->lock);
       |                                               |-> remove ifa->if_list from idev->addr_list
       |                                               |-> write_unlock(&idev->lock);

[28055.378524] ------------[ cut here ]------------
[28055.378591] WARNING: at net/ipv6/addrconf.c:546 inet6_ifa_finish_destroy+0x98/0xc8()
[28055.378691] [<c010de1c>] (unwind_backtrace+0x0/0x144) from [<c09fd08c>] (dump_stack+0x20/0x24)
[28055.378747] [<c09fd08c>] (dump_stack+0x20/0x24) from [<c0192adc>] (warn_slowpath_common+0x58/0x70)
[28055.378840] [<c0192adc>] (warn_slowpath_common+0x58/0x70) from [<c0192bec>] (warn_slowpath_null+0x2c/0x34)
[28055.378931] [<c0192bec>] (warn_slowpath_null+0x2c/0x34) from [<c0911a90>] (inet6_ifa_finish_destroy+0x98/0xc8)
[28055.379026] [<c0911a90>] (inet6_ifa_finish_destroy+0x98/0xc8) from [<c091498c>] (addrconf_ifdown+0x2e4/0x430)
[28055.379120] [<c091498c>] (addrconf_ifdown+0x2e4/0x430) from [<c0915b70>] (addrconf_notify+0xe4/0x3ac)
[28055.379209] [<c0915b70>] (addrconf_notify+0xe4/0x3ac) from [<c01b9df0>] (notifier_call_chain+0x54/0x94)
[28055.379321] [<c01b9df0>] (notifier_call_chain+0x54/0x94) from [<c01ba3ac>] (__raw_notifier_call_chain+0x24/0x2c)
[28055.379379] [<c01ba3ac>] (__raw_notifier_call_chain+0x24/0x2c) from [<c01ba3dc>] (raw_notifier_call_chain+0x28/0x30)
[28055.379475] [<c01ba3dc>] (raw_notifier_call_chain+0x28/0x30) from [<c0840ea4>] (call_netdevice_notifiers+0x38/0x60)
[28055.379568] [<c0840ea4>] (call_netdevice_notifiers+0x38/0x60) from [<c0844d5c>] (__dev_notify_flags+0x3c/0x6c)
[28055.379657] [<c0844d5c>] (__dev_notify_flags+0x3c/0x6c) from [<c0844dcc>] (dev_change_flags+0x40/0x58)
[28055.379747] [<c0844dcc>] (dev_change_flags+0x40/0x58) from [<c08d2834>] (devinet_ioctl+0x79c/0x8bc)
[28055.379837] [<c08d2834>] (devinet_ioctl+0x79c/0x8bc) from [<c08d3488>] (inet_ioctl+0x1c0/0x1d0)
[28055.379928] [<c08d3488>] (inet_ioctl+0x1c0/0x1d0) from [<c082d7f0>] (sock_ioctl+0x80/0x248)
[28055.379982] [<c082d7f0>] (sock_ioctl+0x80/0x248) from [<c0275364>] (do_vfs_ioctl+0x94/0x5bc)
[28055.380071] [<c0275364>] (do_vfs_ioctl+0x94/0x5bc) from [<c0275908>] (sys_ioctl+0x7c/0x8c)
[28055.380164] [<c0275908>] (sys_ioctl+0x7c/0x8c) from [<c0107300>] (ret_fast_syscall+0x0/0x30)
[28055.380252] ---[ end trace 920b8b321354f066 ]---
[28061.735021] Watchdog bark! Now = 28061.735014
[28061.735106] Watchdog last pet at 28050.179294
[28061.735245] cpu alive mask from last pet 0-3
[28061.735321] Causing a watchdog bite!

The addrconf_hash_lock should cover both modification of inet6_addr_list and idev->addr_list
to resolve any possible synchronization issue between addrconf_ifdown() and ipv6_add/del_addr().

Bug: 11293746
Change-Id: If263fc375b411bf21eacade0d094bff95939f7fe
Signed-off-by: David C. Park <davidc.park@lge.com>
msm: set the gdhs to power-collapse to get rid of the IRQ affinity fails.

Change-Id: Ic871a2c5d2cf5171d5c078ae327397e27b3dcbbc
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
cpufreq: cpu-boost: Don't register for cpufreq notifiers too early

The cpufreq notifiers should be registered only after all the data
structures used in the notifier callbacks have been initialized. So, move
the cpufreq notifier registration to a later point in the init function.

Change-Id: I043ab5bc0ebb98164c40549fe151a8d801c8c186
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
msm8974: Update defconfigs for Bacon/Find7

 * Reenable a couple of things we need.

Change-Id: I04a3d6f84aa8d9cc50e055d94a8c7fc70cb98ed2
ARM: 7494/1: use generic termios.h

As pointed out by Arnd Bergmann, this fixes a couple of issues but will
increase code size:

The original macro user_termio_to_kernel_termios was not endian safe. It
used an unsigned short ptr to access the low bits in a 32-bit word.

Both user_termio_to_kernel_termios and kernel_termios_to_user_termio are
missing error checking on put_user/get_user and copy_to/from_user.

Change-Id: I0493d452b8fafe43f06243c2c7f238b56de1aa15
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
vfs: fix bad hashing of dentries

Josef Bacik found a performance regression between 3.2 and 3.10 and
narrowed it down to commit bfcfaa77bdf0 ("vfs: use 'unsigned long'
accesses for dcache name comparison and hashing"). He reports:

 "The test case is essentially

      for (i = 0; i < 1000000; i++)
              mkdir("a$i");

  On xfs on a fio card this goes at about 20k dir/sec with 3.2, and 12k
  dir/sec with 3.10.  This is because we spend waaaaay more time in
  __d_lookup on 3.10 than in 3.2.

  The new hashing function for strings is suboptimal for <
  sizeof(unsigned long) string names (and hell even > sizeof(unsigned
  long) string names that I've tested).  I broke out the old hashing
  function and the new one into a userspace helper to get real numbers
  and this is what I'm getting:

      Old hash table had 1000000 entries, 0 dupes, 0 max dupes
      New hash table had 12628 entries, 987372 dupes, 900 max dupes
      We had 11400 buckets with a p50 of 30 dupes, p90 of 240 dupes, p99 of 567 dupes for the new hash

  My test does the hash, and then does the d_hash into a integer pointer
  array the same size as the dentry hash table on my system, and then
  just increments the value at the address we got to see how many
  entries we overlap with.

  As you can see the old hash function ended up with all 1 million
  entries in their own bucket, whereas the new one they are only
  distributed among ~12.5k buckets, which is why we're using so much
  more CPU in __d_lookup".

The reason for this hash regression is two-fold:

 - On 64-bit architectures the down-mixing of the original 64-bit
   word-at-a-time hash into the final 32-bit hash value is very
   simplistic and suboptimal, and just adds the two 32-bit parts
   together.

   In particular, because there is no bit shuffling and the mixing
   boundary is also a byte boundary, similar character patterns in the
   low and high word easily end up just canceling each other out.

 - the old byte-at-a-time hash mixed each byte into the final hash as it
   hashed the path component name, resulting in the low bits of the hash
   generally being a good source of hash data.  That is not true for the
   word-at-a-time case, and the hash data is distributed among all the
   bits.

The fix is the same in both cases: do a better job of mixing the bits up
and using as much of the hash data as possible.  We already have the
"hash_32|64()" functions to do that.

Change-Id: I3ab5fecae58b1714434c505661a117647287d06f
Reported-by: Josef Bacik <jbacik@fb.com>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Cc: Christoph Hellwig <hch@infradead.org>
Cc: Chris Mason <clm@fb.com>
Cc: linux-fsdevel@vger.kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
arm: compile with the generic rwsem

Change-Id: I5b4a23caf2614067b9b1fbfcaf412ea4f8103f1f
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
Squash 'enhance power efficiency' patches

Series of patches from NVIDIA on some critical blocking
code paths to allow the CPU to relax instead of busy spinning
thus lowering the load_average and lowering power consumption.

Change-Id: Iff80c8c025021874c6d0f6c1ce2e337333b1fd3f
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>