powerpc/T208xRDB: add mtdparts suppport

We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/T1040: add mtdparts suppport for T104xRDB and T1040QDS

We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/cpu/mpc85xx: Add MAC address for layer 2 switch

T1040RDB and T1040QDS boards have an integrated l2 switch.
The switch needs a MAC address for Layer 2 protocols
(MSTP, LLDP, LACP, etc). Setting a MAC address on l2switchaddr will add
a MAC in device-tree, under node l2switch.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
board/t104xrdb: Add support of CPLD

T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.

This support of CPLD includes
 - files and register defintion
 - Commands to swtich alternate bank and default bank

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
fsl/usb: Increase TXFIFOTHRESH value for usb write in T4 Rev 2.0

Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0.
This decreases data burst rate with which data packets are posted from the TX
latency FIFO to compensate for latencies in DDR pipeline during DMA.
This avoids Tx buffer underruns and leads to successful usb writes

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
driver/net/fm/memac_phy: Initialize mdio_clock for SoCs wih FMANv3

MDIO clock needs to be initialized in u-boot code for SoCs
having FMAN-v3(v3H or v3L) controller due to below reasons

-On SoCs that have FMAN-v3H  like B4860, default value of
MDIO_CLK_DIV bits in mdio_stat(mdio_cfg) register generates
mdio clock too high (much higher than 2.5MHz), violating the
IEEE specs.
-On SOCs that have FMAN-v3L like T1040, default value of
MDIO_CLK_DIV bits is zero, so MDIO clock is disabled.

So, for proper functioninig of MDIO, MDIO_CLK_DIV bits needs to
be properly initialized.
Also this type of initialization is generally done in
PBI(pre-bootloader) phase using rcw.But for chips like T1040
which support deep-sleep, such type of initialization cannot be
done in PBI phase due to the limitation that during deep-sleep
resume, FMAN (MDIO) registers are not accessible in PBI phase.
So, mdio clock initailization must be done as part of u-boot.

This initialization code is implemented in memac_phy.c which
gets compiled only for SoCs having FMANv3, so no extra compilation
flag is required.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
drivers/ddr: Fix possible out of bounds error

This is a theoretical possible out of bounds error in DDR driver. Adding
check before using array index. Also change some runtime conditions to
pre-compiling conditions.

Signed-off-by: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
mpc85xx: Add support for the supplement configuration unit register

The supplement configuration unit (SCFG) provides chip-specific
configuration and status registers for the device. It is the chip
defined module for extending the device configuration unit (DCFG)
module. It provides a set of CCSR registers in addition to those
available in the device configuration unit.
The base address for this unit is 0x0F_C000.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
mpc85xx/t104x: Add deep sleep framework support

When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
mpc85xx: Add deep sleep support on T1040QDS

Add deep sleep support on T1040QDS platform.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
mpc85xx: Add deep sleep support on T104xRDB

Add deep sleep support on T104xRDB platforms.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T1040QDS/U-QE: Add u-qe support to t1040qds

Add u-qe support for t1040qds

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: Remove QE firmware copy from NAND

qe_init() does not use data copied from NAND. Thise code is not tested or
complied causing compilation error during NAND boot

So, remove QE firmware copy from NAND to ddr.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
board/t1042rdb_pi: Disable CONFIG_QE and CONFIG_U_QE

T1042RDB_PI board does not have QE connector.

So disable CONFIG_QE and CONFIG_U_QE for T1042RDB_PI

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: Move LAW_EN define outside of config

LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to
CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence
both are same. This cause compilation error.

So LAW_EN define outside of configs

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: Avoid hardcoding in SPL linker script

SPL linker has fix location of bootpg and reset vector with respect to text base.
It is not necessary to have fixed locations.

Avoid such hardcoding.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
powerpc:Add support of SPL non-relocation

Current SPL code base has BSS section placed after reset_vector. This means
they have to relocate to use the global variables. This put an implicit
requirement of having SPL size = Memory/2.

To avoid relocation:
	- Move bss_section within SPL range
	- Modify relocate_code()

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx:Disable non DDR LAWs before init_law

Before parsing LAW table i.e. init_law, boot loader should disable all
previous LAWs except DDR LAWs which has been created by previous
pre boot loader during DDR initialization.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
driver/ifc: define nand_spl_load_image() for SPL

nand_spl_load_image() can also be used for non TPL framework.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
driver/mtd/spi:Read 8KB data chunk during u-boot load in SPL

SPI driver perform its operation(read/write) on 64KB buffer chunk for data
greater than 64KB. This buffer chunk is allocated from system heap.

During SPL boot, 768KB of data is read from SPI flash.
Here, heap size may not be sufficient enough to full-fill 64KB buffer
requirement of SPI driver. So break down u-boot read operation at 8KB of chunk.

Also, fix a warning i.e. "unused variable buf" during CONFIG_FSL_CORENET

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>