headergen2: make things static
rnndec: couple fixes
a3xx: fast-clear depth bit
a3xx: vtx swap bits
rnndec: fix potential segfault
hdmi: add more 8960 phy regs

For upstream kernel, we need to program the hdmi phy pll, since that
isn't hacked in behind the clk API.

See clock-dss-8960.c in downstream kernel.
a4xx: more registers
WIP: rnn: add support for dynamic offset(s)

Variation of "offset"/"offsets" but which are dynamic (ie. to handle
cases where register offsets differ between generation).
WIP: headergen2: add support for dynamic offset(s)
WIP: rnndb: move reg_.. bitset definitions to common MDP xml file

Since reg_wh and reg_xy are used in both mdp4.xml and mdp5.xml,
let's define them in mdp_common.xml which is included by these
two files.

Change-Id: Ided6d240913866c047dde131a65a53617d2faeaf
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
WIP: rnndb: add support for MDP5 v1.3 using dynamic offsets

In order to deal with offsets differences between MDP5 v1.3 and
earlier versions, dynamic offsets are introduced.
At runtime, MDP version is read to find out which hardware
configuration is embedded on the target. Once this is found out,
these dynamic offsets are set through global variables
initializations.
The number of instances for vig/rgb pipes,  LM, DSPP is increased
in v1.3.
This change reflects this hardware configuration and makes the
corresponding registers accessible.

Change-Id: Idaf713427825900866d308896679394228d80601
Signed-off-by: Stephane Viau <sviau@codeaurora.org>