tuna: don't use thermal framework yet, it needs twl6030 gpadc
I2C: OMAP2+: Introduce I2C IP versioning constants

These represent the two kinds of (incompatible) OMAP I2C
peripheral unit in use so far.

The constants are in linux/i2c-omap.h so the omap i2c driver can have
them too.

Change-Id: I42d2c7822985a9bc4124986d7cd786565006466f
Cc: patches@linaro.org
Cc: Ben Dooks <ben-linux@fluff.org>
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andy Green <andy.green@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>

Conflicts:
	arch/arm/plat-omap/include/plat/i2c.h
ARM: OMAP4: Add resistor selection code to the I2C platform driver

Add a call into the I2C to set the I2C pullup resistor strength.

Change-Id: I0bb9eee666d75e04ebd752cb15f1c41a9c8a7b71
Signed-off-by: Dan Murphy <dmurphy@ti.com>

Conflicts:
	arch/arm/plat-omap/i2c.c
OMAP: hwmod: fix the i2c-reset timeout during bootup

The sequence of _ocp_softreset doesn't work for i2c. The i2c module has a
special sequence to reset the module. The sequence is
 - Disable the I2C.
 - Write to SOFTRESET bit.
 - Enable the I2C.
 - Poll on the RESETDONE bit.
The sequence is implemented as a function and the i2c_class is updated with
the correct 'reset' pointer.  omap_hwmod_softreset function is implemented
which triggers the softreset by writing into sysconfig register. On following
this sequence, i2c module resets properly and timeouts are not seen.

Change-Id: I742f18d6db724235a38923312be64723316c9ef1
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: Avinash.H.M <avinashhm@ti.com>
[paul@pwsan.com: combined this patch with a patch to remove
 HWMOD_INIT_NO_RESET from the 44xx hwmod flags; change register
 offset conditional code to use the IP block revision; minor code
 cleanup]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>

Conflicts:
	arch/arm/plat-omap/include/plat/i2c.h
OMAP3+: HWMOD: Add the default clockactivity for I2C

For I2C clockactivity field is added for OMAP3 and OMAP4 that defines how the
interface (OCP) and functional (system) clocks behave when the I2C module is
idle.

The configuration of the clock activity bit field (per TRM) is as follows:
0x0: Both clocks can be cut off
0x1: Only OCP clock must be kept active; system clock
     can be cut off
0x3: Both clocks must be kept active
0x2: Only system clock must be kept active; OCP clock
     can be cut off

The patch makes 0x2 the default for OMAP3 and OMAP4.

Change-Id: Iaa27250ab996becd398a58e8459121e62b384da4
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
OMAP4: PM: Regulator: suspend prepare and finish call.

Before entering suspend configure regulator resource to desired
state.
While resuming from system wide suspend, the  un-connected regulator
resource's are not turned off. By calling regulator_suspend_finish, it
ensures that resources will be gated if the usecount = 0.

Change-Id: I0cff12f24b1c0879fdb27e079baf1c6793f5a1d3
Signed-off-by: Ambresh K <ambresh@ti.com>
OMAP4: PRM: improve cold reset logic

Cold reset logic currently could return back and invoke the
'BUG()' call which was supposed to be triggered if coldreset
was'nt functioning, even though the cold reset is eventually
triggered in h/w this gives a misconception that the cold
reset was'nt really functioning.

In OMAP4, the reset logic could take close to 100uSec before
the cold reset is percolated down from PRCM. Unfortunately,
we dont seem to have a status bit to check exactly when the
PRCM decides to send out cold reset signal to rest of h/w.

The delay is pretty much long enough for kernel messages to
be populated with the 'BUG()' call from pm44xx.c.

Further, it is mandatory that Power On reset bit is cleared
by s/w before cold reset is invoked. This is currently being
done by bootloader/PPA.

Change-Id: I886c420b6532e594b67da6a12122cac785ed6df6
Signed-off-by: Nishanth Menon <nm@ti.com>
omap4: add 4430 ES2.3 support

And default to 4430 ES2.3 for unidentified silicon.

Change-Id: I06b0aa9c5f33af25345996cf9d0c994491093096
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
ARM: OMAP4: Fix OMAP4430 ES2.2 identification

There is a break statement missing in the switch statement for ES2.2
devices that will cause ES2.2 devices to be detected as ES2.3.

Change-Id: I0e02ac4303015e843026c7fb3fb5b6f9de0ae058
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
OMAP4: HSI: changed Fclk to 192Mhz for OPP100

HSI RX and TX bit rates depend on HSI Functional clock and cannot be higher
than Fclk.
Allowed higher HSI throughputs by enabling 192MHz@OPP100.

Change-Id: I274f0860d48ec79a1331366b8866f883ae372d2f
Signed-off-by: Djamil Elaidi <d-elaidi@ti.com>
OMAP4: mux: fixed false detection of IO wakeup event

omap_hwmod_pad_get_wakeup_status() returns -EINVAL when mux structure is not
found, but this is interpreted as true by callers, which deduce there is a
wakeup event for the pad, which is not the case.

Change-Id: I5769c0cc1ed5fc9578b607325ab2bbf2a9d10c14
Signed-off-by: Djamil Elaidi <d-elaidi@ti.com>
OMAP2+: clock: Fix DPLL clock rounding

Function omap2_dpll_round_rate() succeeds only if it can find exact frequency.
But in current implmentations there are some frequencies that can't be rounded.
Function iterates frequencies that always lower than requested one.
For example 550MHz can be obtain from 38.4MHz reference by M=1375 and N=96,
but the closest MN pair that is tried is 1374/96.

It happens because of flooring scaled_rt_rp variable insted of rounding.
This patch should fix the issue.

Change-Id: Iceadcc695ac3376372b2fdaf29afe8f9454b891f
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP2+: clock: Round clock to the closest possible frequency.

Currently clock is always rounded to frequency that is <= required.
It leads to not the best divider selection if requested frequncy is
slightly lower than the closest possible frequency.

This patch makes the best possible divider to be choosen.

Change-Id: I732dbf3e2c910b041434ded0df78dd6f85b7c7f4
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: PM: Program pwrst of each pwdm as per their supported state

Configure next power state of each power domain based on their
supported state. This will be done one time during initialization of
power_setup function. Device can change their power domain state runtime
based on dev latency requirement.
Also, this API will be called during suspend path as well to make sure each power
domain has been configured the right state before entering OFF transition.

Change-Id: I030f2b5df3186cb147e919d9d98dbcdfc75269a8
Signed-off-by: Gilles-Arnaud Bleu-Laine <gilles@ti.com>
Signed-off-by: Girish S G <girishsg@ti.com>
OMAP4: PM: Correct powerstates initialization sequence

  During initialization of new powerstate item it
should be added into list before it's configuration.

  Initialization of powerstates skiped for CORE, MPU,
CPU0, CPU1 powerdomains. Current implementation caused
incorrect initialization of powerstate at least for
GFX PWRDM because it masked by CORE PWRDM.

We should add powerstate node to list before it will
been initialized.

Change-Id: I2f9274a9ec951eb9f6b54e104a0e14921b61264e
Signed-off-by: Volodymyr Riazantsev <v.riazantsev@ti.com>
Revert "OMAP4: PM: Correct powerstates initialization sequence"

This reverts commit daba1ada9b46cf75f000f4312e2b4787f1012816.
This patch causes power regression in not allowing all power domains
to go into low power states

Signed-off-by: Dan Murphy <dmurphy@ti.com>
OMAP4: PM: Re-factor configuring pwrst settings

Refactoring configure_pwrst to allow setting of pwrdm states from init
and suspend path as well.
This takes care of:
- Allow achievable state to be programmed from init and suspend path
- Error if pwrdm state is not set.
- Remove duplication of code.

Change-Id: I1a42566cc83d67b870e9fe1076522ea8ce7ccb4a
Signed-off-by: Girish S G <girishsg@ti.com>
OMAP4: PM: L3INIT allow only CSwR

L3INIT powerstate supports ON, INA, CSwR and OSwR. If OSwR
is enabled EHCI/remote wakeup feature is broken. Till EHCI
IO wakeup is in place allow only CSwR on L3INIT. Power impact
in idle path will be less than 1mA.

REVISIT: For setting OSwR on L3INIT with proper fix in EHCI for IO
wakeup.

Change-Id: I64ada3a307d6cd81483ce6bba684f166d76868b6
Signed-off-by: Girish S G <girishsg@ti.com>
OMAP4: Enable main inst clock for save to ram.

In HS-devices we must ensure that l3_main_inst
clock is enabled for saveram operation

Change-Id: Id9a5ab013ed99499f0fde89d9251ae5a95a49b45
Signed-off-by: Axel Haslam <axelhaslam@ti.com>
Signed-off-by: Akash Choudhari <akashc@ti.com>
Signed-off-by: Chittim Madhusudan <c-madhu@ti.com>
[IVAHD] Disable HWSUP mode and save power

Enabling HWSUP mode is somehow reducing the performance
of SL2 memory leading to increase in power consumption.
This patch disables it and advertises only SWSUP mode
which seems to improve performance and reduce power
consumed in AV record use-case.

Change-Id: Ie7d06b2a7a8d251820afd63bbb093fa34203c3fa
Signed-off-by: Sundar Raman <sunds@ti.com>