cappuccino/lsu: stay in WRITE state on store_buffer_write

Apart from being one clock cycle faster, this also avoids connecting
the (potentially critical) dbus_ack_i signal to the read enable
input of the store buffer.

In addition to that it also fixes a bug where the lsu_valid
signal would be detached from the storebuffer logic when
the state machine would transition from WRITE->IDLE->WRITE.
Merge branch 'master' of github.com:openrisc/mor1kx into multicore

Conflicts:
	rtl/verilog/mor1kx_lsu_cappuccino.v
cappuccino/lsu: delay store_buffer_atomic one clock cycle

This way it is in sync with the rest of the signals that are
used from the store buffer.