simulator: handle diverging stack cache content and stack cache pointers
hardware: Insert timescale into generated code for simulation.
hardware: Tweaks for SRAM controller.
hardware: Initial version of QDRII+ memory controller.
config: Initial configuration for Stratix V development kit.
config: Remove "ports" tags from configuration files.
hardware: Synthesize with a bit more effort for DE2-70 board.
bootloader: Cleaner code in CMP slave.
hardware, simulator, doc: Support for invalidation of data and method cache.
Stratix V board: config files, top level and quartus project files added for the Stratix V development board and IO add-on board.
Merge branch 'master' of https://github.com/t-crest/patmos
hardware: Refactored EMAC as Chisel black box
tools: No more slowing down of UART transmissions to target.
Ignore some more temporary latex output files and kdevelop files
pasim: increased the default M$ size to 4k
handbook: added exception unit address range to IO-device table
build: Expose variable to control name of file with NoC initialization data.
chisel: registerfile using registers fixed
bootloader: now calling _start() after application return
c: test_cmp.c minor fixes.