target-ppc: Altivec 2.07: vmuluw Instruction

This patch adds the Vector Multiply Unsigned Word Modulo (vmuluwm)
instruction.

The existing VARITH_DO macro is re-used to (trivially) instantiate
the helper code.

Since bits 21-31 of any vmuluwm instruction is 137, the instruction
is coded as a dual to vmulouw (bits 21-31 = 136).

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes

This patch adds the Vector Count Leading Zeroes instructions introduced
in Power ISA Version 2.07 - vclzb, vclzh, vclzw and vclzd.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Vector Population Count Instructions

This patch adds the Vector Population Count instructions introduced in Power
ISA Version 2.07: vpopcntb, vpopcnth, vpopcntw and vpopcntd.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions

This patch adds the Vector Minimum and Maximum Doubleword instructions
that are introduced in Power ISA Version 2.07.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Pack Doubleword Instructions

This patch adds the Vector Pack Doubleword instructions introduced in
Power ISA Version 2.07:

 - Vector Pack Signed Doubleword Signed Saturate (vpksdss)
 - Vector Pack Signed Doubleword Unsigned Saturate (vpksdus)
 - Vector Pack Unsigned Doubleword Unsigned Modulo (vpkudum)
 - Vector Pack Unsigned Doubleword Unsigned Saturate (vpkudus)

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Unpack Signed Word Instructions

This patch adds the Unpack Signed Word instructions introduced in
Power ISA Version 2.07:

  - Vector Unpack High Signed Word (vupkusw)
  - Vector Unpack Low Signed Word (vupklsw)

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Vector Merge Instructions

This patch adds the Vector Merge Even Word (vmrgew) and Vector
Merge Odd Word (vmrgow) instructions introduced in Power ISA
Version 2.07.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and Shifts

Existing code in the VROTATE, VSL and VSR macros for the Altivec rotate and shift
helpers uses a formula to compute a bit mask used to extract the rotate/shift
amount from the VRB register.  What is desired is:

    mask = (1 << (3 + log2(sizeof(element)))) - 1

but what is implemented is:

    mask = (1 << (3 + (sizeof(element)/2))) - 1

This produces correct answers when "element" is uint8_t, uint16_t or uint_32t.  But
it breaks down when element is uint64_t.

This patch corrects the situation.  Since the mask is known at compile time, the
macros are changed to simply accept the mask as an argument.

Subsequent patches in this series will add double-word variants of rotates and
shifts and thus take advantage of this fix.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift Instructions

This patch adds the vector doublword rotate and shift instructions
introduced in Power ISA Version 2.07:

  - Vector Rotate Left Doubleword instruction (vrld)
  - Vector Shift Left Doubleword (vsld)
  - Vector Shift Right Doubleword (vsrd)
  - Vector Shift Right Algegbraic Doubleword (vsrad)

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Quadword Addition and Subtracation

This patch adds the Vector Quadword Addition and Subtraction instructions
introduced in Power ISA Version 2.07:

  - Vector Add Unsigned Quadword Modulo (vadduqm)
  - Vector Add & Write Carry Unsigned Quadword (vaddcuq)
  - Vector Add Extended Unsigned Quadword (vaddeuqm)
  - Vector Add Extended & Write Carry Unsigned Quadword (vaddecuq)
  - Vector Subtract Unsigned Quadword Modulo (vsubuqm)
  - Vector Subtract & Write Carry Unsigned Quadword (vsubcuq)
  - Vector Subtract Extended Unsigned Quadword (vsubeuqm)
  - Vector Subtract Extended & Write Carry Unsigned Quadword (vsubecuq)

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: vbpermq Instruction

This patch adds the Vector Bit Permute Quadword (vbpermq) instruction
introduced in Power ISA Version 2.07.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Doubleword Compares

This patch adds the Vector Compare Doubleword instructions introduced
by Power ISA Version 2.07:

  - Vector Compare Equal to Unsigned Doubleword (vcmpequd)
  - Vector Compare Greater Than Signed Doubleword (vcmpgtsd)
  - Vector Compare Greater Than Unsigned Doubleword (vcmpgtud)

These instructions are encoded with bit 31 set to 1 and so are duals with
vcmpeqfp, vcmpgtfp and vcmpbfp respectively.

The helper macro for integer compares is enhanced to account for 64-bit
operands.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Vector Gather Bits by Bytes

This patch adds the Vector Gather Bits by Bytes Doubleword (vgbbd)
instruction which is introduced in Power ISA Version 2.07.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum

This patch adds the Vectory Polynomial Multiply Sum instructions
introduced in Power ISA Version 2.07:

  - Vectory Polynomial Multiply Sum Byte (vpmsumb)
  - Vectory Polynomial Multiply Sum Halfword (vpmsumh)
  - Vectory Polynomial Multiply Sum Word (vpmsumw)
  - Vectory Polynomial Multiply Sum Doubleword (vpmsumd)

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Binary Coded Decimal Instructions

This patch add the Binary Coded Decimal instructions bcdadd. and
bcdsub.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: AES Instructions

This patch adds the Vector AES instructions introduced in Power ISA
Version 2.07:

   - Vector AES Cipher (vcipher)
   - Vector AES Cipher Last (vcipherlast)
   - Vector AES Inverse Cipher (vncipher)
   - Vector AES Inverse Cipher Last (vncipherlast)
   - Vector AES SubBytes (vsbox)

Note that the implementation of vncipher deviates from the RTL in
ISA V2.07.  However it does match the verbal description in the
third paragraph.  The RTL will be fixed in ISA V2.07B.  The
implementation here has been tested against actual P8 hardware.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Vector SHA Sigma Instructions

This patch adds the Vector SHA Sigma instructions introduced in Power
ISA Version 2.07:

  - Vector SHA-512 Sigma Doubleword (vshasigmad)
  - Vector SHA-256 Sigma Word (vshasigmaw)

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Altivec 2.07: Vector Permute and Exclusive OR

This patch adds the Vector Permuate and Exclusive OR (vpermxor)
instruction introduced in Power ISA Version 2.07.

Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
spapr-vlan: flush queue whenever can_receive can go from false to true

When the guests adds buffers to receive queue, the network device
should flush its queue of pending packets. This is done with
qemu_flush_queued_packets.

This adds a call to qemu_flush_queued_packets() which wakes up the main
loop and let QEMU update the network device status which now is "can
receive". The patch basically does the same thing as e8b4c68 does.

Suggested-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc/translate.c: Use ULL suffix for 64 bit constants

64 bit constants need the "ULL" suffix, not just "UL", because
on 32 bit platforms 'long' is not large enough and this will
cause a compiler warning.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Alexander Graf <agraf@suse.de>