fix bugs in re-done VICIV char fetch FSM.
fix bug preventing fetching of screen RAM bytes.
first two columns of text and screen colour are wrong, however.
add screen_ram_buffer_address to VIC-IV debug registers.
add extrea VIC-IV debug register and comments.
flatten CPU logic to improve timing.
big table dropped maximum clock to 65MHz, so need to rethink that.
begin implementing single-cycle instructions (CLC and SEC tested).
set reg_opcode for visibility in serial monitor.
implement some more single cycle instructions and incrementer
functions.