Multicore: Add core identifier

The core identifier can be read from SPR group 0 (system) at address
128 (newly assigned). Furthermore it is possible to read the number of
processor cores in a cluster via register 129. Both can apparently not
be written.

The registers are set via ports, which allow easier use in verilated
models or similar.
Merge branch 'master' into multicore
Merge remote-tracking branch 'openrisc/master' into multicore
WIP: add support for l.lwa/l.swa atomic instructions
cappucino-ctrl: Add two ISRs in multicore mode

We need something like shadow registers in multicore mode as we need
to do clean calculations on exceptions. Add two ISRs (ISR0 and ISR1)
which are used as scratch registers on exceptions.
Debug: Execution traceport

The execution traceport traces all executed program counters, the
respective instruction and accesses to the register file with this
instruction. A rudimentary set of trace actions can be implemented in
a synthesizable way.

Set FEATURE_TRACEPORT_EXEC="ENABLED" to enable this trace port.

Add monitor for simulation.
WIP: Add snoop port