Fix 'dram_clk' reporting for frequencies that are not multiples of 24

The K and M factors encode values 1-4 in two bits (starting from 1
and not 0). The typical DRAM clock frequency setup uses K=2 and M=2,
which means that both of them are read as 1 from the bit fields.
That's why a10-meminfo used to work in most cases (1/1 is the same
as 2/2). However a10-meminfo happens to report wrong 'dram_clk' if
the other values of K and M are selected. This patch fixes it.
Identify and report MBUS clock speed

MBUS clock speed is important for memory performance on
Allwinner A20. So it makes sense to also report it.