Slight tweaks plus comments.
Use a much simpler x86 lowering mechanism.

This one avoids using the local register manager entirely, and instead
generates lots of temporaries.  For example, "a=b+c" becomes
  temp=b
  temp+=c
  a=c

And an address mode optimized load "a=[b+4*c]" becomes
  temp1=b
  temp2=c
  a=[temp1+4*temp2]

The temporaries are given an effectively infinite weight to guarantee
that the register allocator will not spill them.

In the "load" example, if b and c's live ranges extend beyond the load
instruction, we see a problem where temp1 and b interfere, and temp2
and c interfere, and they all get different registers.  To fix this,
we allow temp1 to be "linked" to b and temp2 linked to c, meaning that
when considering temp1's live range, we can assign it b's register
(assuming b actually has a register).

There is still an unpleasant amount of register shuffling due to phi
lowering.  Hopefully this can be helped later perhaps from some
combination of phi assignment placement and register allocator hints.