target-mips: fix tlb->PFN to contain actual Page Frame Number

This modification will prevent >32-bits from being truncated in r4k_fill_tlb
due to left shift on MIPS32 target.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: extend EntryLo0/1, LLAddr and TagLo to 64-bits in MIPS32

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: update tlb->PFN to contain PFN concatenated with PFNX

PFNX is always 0 on a core without large physical address support.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: add PageGrain.ELPA and use env->PAMask

PageGrain.ELPA enables support for large physical addresses. This field
is encoded as follows:
0: Large physical address support is disabled.
1: Large physical address support is enabled (XPA).

If this bit is a 1, the following changes occur to coprocessor 0 registers:
- The PFNX field of the EntryLo0 and EntryLo1 registers is writable and
  concatenated with the PFN field to form the full page frame number.
- Access to optional COP0 registers with PA extension, LLAddr, TagLo is defined.

P5600 can operate in 32-bit or 40-bit Physical Address Mode. Therefore if XPA
is disabled (PageGrain.ELPA = 0) then assuming 32-bit Address Mode.

Leaving MIPS64 with default 36 PABITS.

env->PABITS value is constant and indicates maximum PABITS available on a core,
whereas env->PAMask is calculated from env->PABITS and is also affected by
PageGrain.ELPA (in MIPS32 core PABITS >32 are ignored if ELPA is disabled).

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: add MTHC0 and MFHC0 for MIPS32

The MIPS32r5 architecture adds two new instructions for accessing the upper
32-bits of the selected 64-bit CP0 register.

The MFHC0 instruction performs a move-from-high Coprocessor 0 operation which
moves the contents from the upper 32-bits of a coprocessor 0 register that has
been extended by 32-bits, to a generate purpose register.

The MTHC0 instruction performs a move-to-high Coprocessor 0 operation which
moves the contents of a general register to the upper 32-bits of a coprocessor 0
register that has been extended by 32-bits.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: update mips32r5-generic to support XPA

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Merge pull request #5 from lalrae/xpa-mips32r5

add XPA feature