i2c-bridge: Updated bridge and slave modules

Bridge: Removed "redundant" SIM_WB_TRANSFER state.

Slave: Removed redundant ADDR_CHECK state and moved its code to
the ADDR state.

Also corrected a bug whereby the ack_i pin was not being checked within
the ADDR_ACK state. This was causing the FSM to advance even thogh the
slave was actually NACK-ing.

DOC: Updated documentation for both these modules

Signed-off-by: Theodor Stana <t.stana@cern.ch>
multiboot: Updated wbgen2 file for documentation

Also updated the rest of the documentation file to have a pretty
regmap.

Signed-off-by: Theodor Stana <t.stana@cern.ch>
switch-optimization: generic to disable virtex6 fifo utilization counting
fix almost_full threshold for Virtex6 FIFO

Xilinx defines almost full threshold not as the used words in the FIFO but as
number of available empty words (UG363 - Virtex 6 FPGA Memory Resources
inferred_async_fifo: Assigned full and almost full and empty outputs in all clock domains

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Moved sync chain out of gc_glitch_filt, added gc_glitch_filt doc

To make the design more modular, moved the synchronization chain out of
the gc_glitch_filt component. Made the necessary changes in the
components using the gc_glitch_filt.

Also added gc_glitch_filt documentation.

Signed-off-by: Theodor Stana <t.stana@cern.ch>
fix almost_full threshold for Virtex6 FIFO also in generic_async_fifo
wb_i2c_bridge: Make FSM watchdog setup more generic

This is done by adding a generic to the entity, which is connected directly to
the gc_fsm_watchdog component instantiated within the wb_i2c_bridge. The user
should calculate the appropriate watchdog timeout value and set it via this
generic.

The instantiation template in the wishbone_pkg is also updated.

Signed-off-by: Theodor Stana <t.stana@cern.ch>
doc: Update wb_i2c_bridge and add colored tables to other modules

Signed-off-by: Theodor Stana <t.stana@cern.ch>
hdl/modules/wishbone/*: add f_wb_wr() funtction

The Ethretbone core uses this function, but
it is not defined within its own repository.

As a temporary fix, we declare this function in
the wishbone_pkg.vhd file, while this is addressed
by the Etherbone team.
hdl/genrams/*: add 7SERIES fifo wrappers

Actually, it was just copied from the VIRTEX6
package and the string "v6" change to "s7".
Probably, there are some differences between the
two FIFOs that are not considered now, but it will
soon.
modules/genrams/xilinx/*: use grounded srstreg

The attributes DO_REG and EN_SYN are always
complementary to each other. So, when one of
them is 1 (or true) the other is 0 (or false)
and vice-versa.

However, as per Xilinx documentation and my own
experience (errors on Xilinx bitgen), in order to
use the RSTREG signal, both of them need to be 1
(or true), which is never the case for the current
mapping.

A fix is to ground the "srstreg" signal, as we never
have the necessary combination of attributes to use it,
anyway.