[r2dbe_top] Added pipeline delays to r2dbe_top and to the
r2dbe_vdif_lib to achieve timing closure on the r2dbe_top
design

In the vdif block I added pipeline delays around software
registers to achieve better timing.

To the r2dbe_top I did the same, but some of these changes
were needed in the casper library snap blocks.  The blocks
in their library form have just delays rather than pipeline
delays, and as these paths produces negative slack they had
to be adjusted.  I broke the link on these blocks, but perhaps
they should be pushed and committed to the greater mlib_devel.
I will leave that decision for another time, in the event
it breaks something in other designs that I have not forseen.

The addition of delays brought failing paths down from 200 to
4.  The 4 remaining failing paths were due to the fact that my
"startsg" script (not part of mlib_devel, set on your individual
workstation) was not importing the pin allocations for our
particular roach 2 version.  This caused incredibly long paths
within the adc blocks, as they were routing zdock signals from
incorrect and far away pins.  This correction produced a design
that meets timing at 256 MHz.

This design is untested at the moment, as I need to adjust lab
bench settings to produce a 256 MHz clock via the ADCs.  Previous
tests used sys_clock.