msm: kgsl: Restructure offset definitions for IOMMU registers

Define the IOMMU register offsets in a structure array. This
offers flexibility in defining  IOMMU v2 offsets in another array
and the right array to be used can be setup during MMU
initialization.

Also, restrict the usage of IOMMU offsets only in the iommu file
by redifining the functions that return iommu information. Remove
the function to get iommu mapped register address and replace
it with a function that returns the gpuaddress of given iommu
register. Only return the valid address bits of an iommu pagetable
instead of just returning the pagetable base register value.

Change-Id: Ib88e605f57e551c7b84029647451cb20f06025a0
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>

Conflicts:

	drivers/gpu/msm/kgsl_mmu.h
msm: kgsl: Updated VBIF settings for A330 to improve performance

Changed values written to VBIF registers for A330.
The maximum pending request from clients is increased to 24.
Disable VBIF clock gating. This potentially increases stand-by power.

Change-Id: Ic9a4f15546f4122298e140e79e4572c82e6385fc
Signed-off-by: Lokesh Batra <lbatra@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
msm: kgsl: Define register offsets for IOMMU-v2

Define the register offsets for IOMMU-v2 and switch off using per
process pagetables for IOMMU-v2.

Change-Id: I8b76de557c8e52b5a2a333ceb987bd743b213eb7
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
msm: kgsl: Do not save context if it is being destroyed

No need to save a context if it is being destroyed since
it will no longer be used at all. This is better for
performance and also avoids the use of legacy kgsl
context save code for contexts that use preambles

Change-Id: I19a64e82188b4132f353bb61c21e4ed2281092fc
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
msm: kgsl: set GPU register RB_GMEM_BASE_ADDR

GPU register RB_GMEM_BASE_ADDR needs to be initialized with GMEM base
address. From A330, OCMEM is utilized to be GMEM dynamically; when
OCMEM is allocated for GFX, the allocated region address may vary
every time, GPU register RB_GMEM_BASE_ADDR need to be initialized
with the allocated OCMEM region address.

Change-Id: I5cb4472a9f18759d2af160a15d83f1404378a530
Signed-off-by: liu zhong <zhongl@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
msm: kgsl: A3xx: Initialize UCHE 64-byte cachelines

For A3xx, initialize UCHE_CACHE_MODE_CONTROL_REG to
0x00000001 so that UCHE will always use 64-byte
cachelines when we boot up or reset. This value
increases performance and was previously set in the
graphics preambles, but should instead be set at
boot/reset time.

Change-Id: Iec71ffc04262ac43534fd632d8b092a48d280509
Signed-off-by: Kevin Matlage <kmatlage@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
msm: kgsl: Increase REG_RBBM_CNTL value to 0xFFFF for A20X

Increase number of clocks that RBBM will wait before de-asserting
the Register Clock Active signal. This fixes kernel panics during
stability tests on multiple devices

Change-Id: I6f7f8bb17cfd9c5beed0fd21d56ab6ab9fd40195
Signed-off-by: Rammohan Basavaraju <rammoh@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
msm: kgsl: Add adreno_is_a330() for A330 specific code

Create adreno_is_a330() to identify the GPU for A330 specific
register settings and core specific code.

Change-Id: Ic0dedbade244ffba3ba3917661a88f97108e6182
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
msm: kgsl:  Adjust the size of the ROQ buffer based on GPU core

The A330 has a larger ROQ buffer then the A305/A320 variants so
adjust the size at runtime based on the core type.

Change-Id: Ic0dedbade62c988cfe402876bc94d91a2dd71617
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
msm: kgsl: A330: Dump the CP_MERCIU block in the snapshot

The CP MERCIU queue can be read from the A330 GPU. Dump it into
the snapshot binary.

Change-Id: Ic0dedbadf2c61ccec6a11af103374f4aee8be727
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
msm: kgsl: Pass multiple register sets to the snapshot register dump

Expand the snapshot register dump helper function to support multiple
sets of registers.  This will be useful for derivative GPUS that
use a global subset of registers and add a few new ones.  This will
not be useful for chipsets that have extensive changes to existing
registers.

Change-Id: Ic0dedbad05bcc3b5a3a0cc933659959965ff5817
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
msm: kgsl: Add subset of new A330 registers

The A330 GPU defines a few new registers that don't exist on
A305/A320.  Define a new subset for A330 and dump it in the
postmortem and binary snapshot.

Change-Id: Ic0dedbadd0c44ee8872b99fd6b0b3dc8eb972eea
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
msm: kgsl: Invalidate base pointers when tlb is flushed

Invalidate the base pointer even when tlb is flushed. For
gpummu the base pointers are invalidated even after just
a tlb flush, with IOMMU do the same.

Change-Id: I11c7d4b841e5f8becd30a087bcabc0ae69c3fee5
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
msm: kgsl: Handle missed alloc error cases

There is a chance that we could fail to allocate memory and then write
to it when allocating entries for our scatter gather list.  Handle the
error cases properly to prevent writing to NULL.

Change-Id: I33978ff53114ede7007b3240406583bcbef2f292
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>
msm: kgsl: unprepare clocks when we move from NAP to SLEEP

The existing code leaves clks prepared when we transition from
NAP to SLEEP. We fail to reach Vdd_min as voltage scaling has
moved to prepare/unprepare.

Change-Id: I509f4c6bd217ead985890147819236dd2c5d03ce
Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>