Use 'sizeof(data)' rather than '4' when checking an mbuf bound, as is the
case for adjusting length/etc.
Break out atse_intr() into two separate routines, one for each of the two
interrupt sources: receive and transmit.  For now, retain an
atse_start_locked() in the receive-interrupt path to reduce latency in
certain cases.  After we adjust FIFO behaviour, we can hopefully drop
this.
Various improvements to atse:

For the RX interrupt, take interest only in ALMOSTEMPTY and OVERFLOW.

For the TX interrupt, take interest only in ALMOSTFULL and UNDERFLOW.

Perform TX atse_start_locked() once rather than twice in TX interrupt
handling -- and only if !FULL, rather than unconditionally.

Simplify interrupt code some.
Experimentation suggests that the Altera Triple-Speed Ethernet documentation
is incorrect and bits in the event and interrupt-enable registers are not
irrationally rearranged relative to the status register.
Substantially rework interrupt handling in the atse(4) driver:

- Introduce a new macro ATSE_TX_PENDING() which checks whether there is
  any pending data to transmit, either in an in-progress packet or in
  the TX queue.
- Introduce new ATSE_RX_STATUS_READ() and ATSE_TX_STAUTS_WRITE() macros
  that query the FIFO status registers rather than event registers,
  offering level- rather than edge-triggered FIFO conditions.
- For RX, interrupt only on full/overflow/underflow; for TX, interrupt
  only on empty/overflow/underflow.
- Add new ATSE_RX_INTR_READ() and ATSE_RX_INTR_WRITE() macros useful for
  debugging interrupt behaviour.
- Add a debug.atse_intr_debug_enable sysctl that causes various pieces
  of FIFO state to be printed out on each RX or TX interrupt.  This is
  disabled by default but good to turn on if the interface appears to
  wedge.  Also print debugging information when polling.
- In the watchdog handler, do receive, not just transmit, processing, to
  ensure that the rx, not just tx, queue is being handled -- and, in
  particular, will be drained such that interrupts can resume.
- Rework both atse_rx_intr() and atse_tx_intr() to eliminate many race
  conditions, and add comments on why various things are in various
  orders.  Interactions between modifications to the event and interrupt
  masks are quite subtle indeed, and we must actively check for a number
  of races (e.g., event mask cleared; packet arrives; interrupts enabled).
  We also now use the status registers rather than event registers for
  FIFO status checks to avoid other races; we continue to use event
  registers for underflow/overflow.

With this change, interrupt-driven operation of atse appears (for the
time being) robust in my CHERI test setup.  Leave polling as the default
for now.  In general, I would characterise the Altera FIFOs as "quite
hard to work with correctly from software" leading me to suspect that
some further refinement of this code will be required.