Lazily link GlobalVariables and GlobalAliases.

We were already lazily linking functions, but all GlobalValues can be treated
uniformly for this.

The test updates are to ensure that a given GlobalValue is still linked in.

This fixes pr21494.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223681 91177308-0d34-0410-b5e6-96231b3b80d8
Clean up the rst for the debug info tutorial

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223682 91177308-0d34-0410-b5e6-96231b3b80d8
ConstantFold: Zero-sized globals might land on top of another global

A zero sized array is zero sized and might share its address with
another global.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223684 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Move continue after checking s_mov_b32.

There's nothing else to bother trying to shrink these.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223686 91177308-0d34-0410-b5e6-96231b3b80d8
Make myself the code owner for llgo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223691 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh/sat/<<16 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223692 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Adding xtype parity, min, minu, max, maxu instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223693 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Adding xtype doubleword comparisons.  Removing unused multiclass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223701 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Adding xtype doubleword add, sub, and, or, xor and patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223702 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Fixing broken test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223704 91177308-0d34-0410-b5e6-96231b3b80d8
[PowerPC] Don't use a non-allocatable register to implement the 'cc' alias

GCC accepts 'cc' as an alias for 'cr0', and we need to do the same when
processing inline asm constraints. This had previously been implemented using a
non-allocatable register, named 'cc', that was listed as an alias of 'cr0', but
the infrastructure does not seem to support this properly (neither the register
allocator nor the scheduler properly accounts for the alias). Instead, we can
just process this as a naming alias inside of the inline asm
constraint-processing code, so we'll do that instead.

There are two regression tests, one where the post-RA scheduler did the wrong
thing with the non-allocatable alias, and one where the register allocator did
the wrong thing. Fixes PR21742.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223708 91177308-0d34-0410-b5e6-96231b3b80d8
[PowerPC]Activate FeatureVSX for the Power target

This change activates FeatureVSX for Power 7 and Power 8 in PPC.td.

http://reviews.llvm.org/D6570


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223709 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Adding any8, all8, and/or/xor/andn/orn/not predicate register forms, mask, and vitpack instructions and patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223710 91177308-0d34-0410-b5e6-96231b3b80d8
MISched: Fix moving stores across barriers

This fixes an issue with ScheduleDAGInstrs::buildSchedGraph
where stores without an underlying object would not be added
as a predecessor to the current BarrierChain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223717 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Removing old def versions and replacing usages with versions that have encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223720 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Move setting of the lds bit to the base MUBUF class

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223721 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Set MayStore = 0 on MUBUF loads

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223722 91177308-0d34-0410-b5e6-96231b3b80d8
Add argument variable support to the debug info tutorial
and rearrange the prologue source location hack to immediately
after it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223725 91177308-0d34-0410-b5e6-96231b3b80d8
Handle early-clobber registers in the aggressive anti-dep breaker

The aggressive anti-dep breaker, used by the PowerPC backend during post-RA
scheduling (but is available to all targets), did not handle early-clobber MI
operands (at all). When constructing the list of available registers for the
replacement of some def operand, check the using instructions, and remove
registers assigned to early-clobbered defs from the set.

Fixes PR21452.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223727 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r223709, "[PowerPC]Activate FeatureVSX for the Power target", to unbreak bots.

CodeGen/PowerPC/vsx-p8.ll was failing.

  '+power8-vector' is not a recognized feature for this target (ignoring feature)
  llvm/test/CodeGen/PowerPC/vsx-p8.ll:33:14: error: expected string not found in input
  ; CHECK-REG: lxvw4x 34, 0, 3
               ^
  <stdin>:50:2: note: scanning from here
   .align 3
   ^
  <stdin>:61:2: note: possible intended match here
   lvx 3, 0, 3
   ^

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223729 91177308-0d34-0410-b5e6-96231b3b80d8