Converting RTL to SystemVerilog:
- Use always_comb and always_ff
- Use structs for l2req and l2rsp
- Use enums where applicable
- Switch regs and wires to logic
- Get rid of assert_false module and use assert()
- Use 'unique case' and 'priority case'
Fix synthesis errors
Fix simulation bug.  Regen autos.
Change loop variables from integer to int and declare inline
Use structs for load miss queue and store buffer entries
Fix handling of L2 write update signals to work properly with multiple cores again.  Remove CLOG2 macro.
Fix some synthesis warnings
Some system verilog conversions: use always_ff/always_comb, integer->int, unique_case and convert enums
Fix synthesis error