Initial VHDL exporter version - does not cater for children or regimes
Intermediate Commit, beginnings of testbench for Simulation
Intermediate Commit, beginnings of testbench for Simulation
New way to traverse the component tree, attempting to convert LEMS without any neuron knowledge
iaf_cell without regimes Simulates as expected - still need to do a LEMS side by side comparison
Testbench Generation functional, test iaf_cell not yet accurate to the lems simulation, also numerical accuracy even in time resolution is lacking.
increased bit widths for voltage and time