aarch64: remove some verbosity from processor.hh

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
aarch64: mmu: distinguish between device and normal memory

we need to do that because load/store instructions
behave differently with Device-nGnRnE memory.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
aarch64: smp: prepare GIC initialization per cpu

arch::init_on_cpu should initialize the gic cpu interface,
but not for the boot CPU, for which this has already been
done.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
aarch64: smp: do not forget to create incoming_wakeups

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
aarch64: implement basic General Timers infrastructure

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
aarch64: implement exception entry and exit

generate exception frame

Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com>
Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
aarch64: arch-switch: implement switch to first

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
aarch64: implement page fault, fixup, backtrace

implement page fault handling, including fixup fault,
and backtrace which is the first simple user.

Signed-off-by: Jani Kokkonen <jani.kokkonen@huawei.com>

[claudio: added elf changes to allow lookup and demangling to work]

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
aarch64: loader: allow execution to main_cont

allow execution to flow until main_cont
so we can reach the backtrace.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
loader: move leftover arch-dependent code to arch

move driver setup and console creation to arch-setup,
and ioapic init for x64 to smp_launch, so that we
can remove ifdefs and increase the amount of common code.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
aarch64: build.mk: enable real bootfs.bin

we start with only a tst-hello.so.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
aarch64: bsd: atomic.h: change atomic_store_rel_int

revert to a simple implementation which is just atomic,
adding a barrier for the compiler.
The store release is used without load acquire.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
XXX aarch64: sched: workaround for tls initialization

XXX workaround for broken initialization of tls vars.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
XXX switch-to and further ahead

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>