msm: mdss: Make notify update waits interruptible

Wait for completion in notify update call are uninterruptible
causing excessive delay during suspend cases. Making them
interruptible.

Change-Id: I1a4ff6ce3e0add21d4e46a41372b076b277d10f5
Signed-off-by: Krishna Chaitanya Parimi <cparimi@codeaurora.org>
msm: mdss: move MDSS revision macros to /linux/msm_mdp.h

Currently kernel driver and user mode libraries keep their own
copies of HW revision numbers. This strategy is prone to errors
and usually frowned upon. Fix this by moving revision information
to sanitized header which is shared by kernel drivers and user mode
libraries.

Change-Id: I59d1256ffd98e07f4ef9ae2b534f04b67abd2119
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
msm: mdss: MDP clock optimization for single layer video playback

MDP core clock bumping is not required for single layer video
playback in 8x26 targets. Hence add revision check to avoid fudge
factor.

Change-Id: I1b0ccb4ef50514f705845b0218fa6ca0d28c1779
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
msm: mdss: Fix mdp clock rate assignment when apply fudge is false

When apply fudge is false, currently mdp clock rate can take
garbage values, hence assign the calculated clock rate without
applying any fudge factors.

Change-Id: I7c9d34024ab94b05160b50560ab136c0c8b7781d
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
msm: mdp3: underflow color adjust support on 8x10

This adds the underflow color adjustment support on
8x10. Customer can order underflow color by modifying
the parameter in panel device tree.

Change-Id: I0660f35e3a0052e5a995256978f354cf30e76161
Signed-off-by: Shuo Yan <shuoy@codeaurora.org>
mdss: mdp3: fix logic when verifying if image can be scaled by 1

There was an issue where images that could be scaled by 1 were not
being blit by ppp due to logic error.

Change-Id: I6f8cdf43d5398a7894e5b7f8a867ec59341345b8
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
mdss: mdp3: Group together resource enable, simplifying xo shutdown

Grouping calls to prepare and unprepare of clocks along with enable
and disable for saving power in the case of static screen on command
mode panels. This makes sure that corresponding source clocks are
also disabled allowing xo shutdown to happen.

On top of that bandwidth request and iommu enable was grouped with
enabling/disabling clocks so that all display related clocks are
disable in static screen allowing for xo shutdown to happen.

Change-Id: I2db3844cbab5c41ea1bb37f5a5ed76c3c63e3a1d
Signed-off-by: Terence Hampson <thampson@codeaurora.org>
ARM: dts: mdss: Add boolean property for LUT readability

LUT read is not supported by hardware in the case of msm8226.
Adding property to dtsi file to denote the absense of support
for read in hardware.

Change-Id: I29cf869af4135e1199bc0feb4369700b994520ec
Signed-off-by: Krishna Chaitanya Parimi <cparimi@codeaurora.org>
msm: mdss: Correct ARGC read write for all DSPP

Currently ARGC read write is done for DSPP0 irrespective of
dspp_num, as the dspp_num corresponding to the block provided
is not calculated.

Added the calculation of the dspp_num to get correct address
of ARGC registers.

Change-Id: Id787e76debb26d23d75d3cdb859a697b6f0016f5
Signed-off-by: Krishna Chaitanya Parimi <cparimi@codeaurora.org>
msm: mdss: Copy IGC LUT data correctly to userspace

During IGC read operation, IGC LUT's data was copied to
userspace incorrectly because of swapping color components.

Fix component data swapping during IGC LUT data copy to
user space to provide the correct IGC LUT data to user space.

Change-Id: I301a3500f0e0c4bbf9f52affa66373585c72d987
Signed-off-by: Krishna Chaitanya Parimi <cparimi@codeaurora.org>
msm: mdss: Reading IGC and PGC LUT from cached values

Certain targets like msm8226 do not have capability of reading
IGC and PGC LUT from hardware registers.
Adding functions to read the LUT values from software cache.

Change-Id: Ifd0f5f131b7ff1fd7d1fb122425241a0e0cec328
Signed-off-by: Krishna Chaitanya Parimi <cparimi@codeaurora.org>
msm: mdss: protect command mode BW votes by tracking HW/SW states

Track two states where the BW is needed for the command mode panels
and prevent the BW vote to be released during any of those two states:
1. SW Commit State: This state is the time when the SW has requested
a BW vote, and it will be processing it; it starts at the beginning of
Commit and finish once the kickoff is issued.
2. HW MDP State: This state is the time when the HW is busy
doing the actual transaction, so bandwidth must be kept until
HW finishes; it starts at the beginning of the kickoff and finishes
once the ping pong done interrupt is received.

Change-Id: I2e56128be3ab25a1b065692ae76387a3cd383df3
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
ion: Add missing unlock on error path

A mutex_unlock was missing for the alloc_lock on an error
path. Add it.

Change-Id: If88b72fbc2fd18504347b784d5daa2bc9170c55f
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
ion: retry during race with shrinking/allocating

There exists a race between shrinking/allocating

Thread 1:                           Thread:2
mutex_lock(&sheap->alloc_lock)
ion_secure_cma_add_to_pool()
mutex_lock(&sheap->chunk_lock)
chunk->cnt = 0
mutex_unlock(&sheap->chunk_lock)
                                    ion_secure_cma_shrinker
                                    mutex_lock(&sheap->chunk_lock)
                                    __ion_secure_cma_shrink_pool
                                    chunk->cnt == 0 for the
                                       just allocated chunk
                                    ion_secure_cma-free_chunk
ion_secure_cma_alloc_from_pool
no memory to allocate!

If this race happens, just retry adding memory to the pool instead
of BUGing out the system.

Change-Id: Ic95782db6d88a33f01dcc5248fc957ca0f378078
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>