Update lz4 files to the latest from GTKWave
vhdlpp: Subprogram class inherits from ScopeBase.
vhdlpp: Added ScopeBase::transfer_from() method.
vhdlpp: Support for variable declarations in subprograms.

Fixes sorrymsg: "variable_declaration not supported."
vhdlpp: Support for std_logic_vector return type in functions.

VHDL does not allow to specify the size of returned std_logic_vector,
whereas Verilog requires the size to be known in advance. The size of
the vector is determined by checking the type of expression used in the
return statement.
vhdlpp: Workaround to avoid translation of variables to wires in functions.
vhdlpp: Subprogram parameters are taken into account when distinguishing between function calls and vector elements.
vhdlpp: Elaboration of ExpFunc parameters fallbacks to the types given in the Subprogram header.
Elaborate root tasks/functions.
vhdlpp: Libraries are searched for subprograms during the ExpFunc elaboration.
Get $root scope tasks/fuctions down to the ivl_target API.
Merge branch 'master' of github.com:steveicarus/iverilog
Merge pull request #45 from orsonmmz/subprogram

Subprograms
Handle functions in $root scope.
Fix parse.y bad handling of file names in some situations.

The YYLLOC_DEFAULT() macro needs to get the .text value even
when the rules are empty.
vhdlpp: ForLoopStatement emits range boundaries expressions instead of evaluating them.

Unfortunately without evaluation it is not possible to warn against
degenerated loops, so it had to be removed.
vhdlpp: Support for 'left & 'right attributes.
vhdlpp: Added ExpAttribute::write_to_stream().
vhdlpp: prange_t may have the direction determined automatically.
vhdlpp: Support for 'range and 'reverse_range attributes.