[mips][mips64r6] bc2[ft] are not available on MIPS32r6/MIPS64r6

Summary:
These instructions are not implemented for any MIPS ISA so we only need
testcases.

Depends on D4110

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4111

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210786 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6

Summary:
Also tightened up the acceptable condition operand for these instructions
on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior
to that only $fcc0 is acceptable.

We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's
probably best to do this in InstCombine.

Depends on D4111

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4112

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210787 91177308-0d34-0410-b5e6-96231b3b80d8
Disable the load/store optimization pass for Thumb-1.

Moritz's changes have improved codegen a lot, but further testing showed significant correctness problems. Disable by default until these have been worked out.

Patch by Moritz Roth!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210789 91177308-0d34-0410-b5e6-96231b3b80d8