fp64: add more constant expression code for pack/unpack + ldexp
nvc0: make sure that the local memory allocation is aligned to 0x10

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
nv50/ir: keep track of whether the program uses fp64
nvc0: mark shader header if fp64 is used

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nv50/ir: fix hard-coded TYPE_U32 sized register

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nv50/ir: fix phi/union sources when their def has been merged

In a situation where double-register values are used, the phi nodes can
still end up being u32 values. They all get merged into one RA node
though. When fixing up the merge (which comes after the phi node), the
phi node's def would get fixed, but not its sources which would remain
at the low register value.

This maintains the invariant that a phi node's defs and sources are
allocated the same register.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
glsl: add a lowering pass for frexp/ldexp with double arguments

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
gallium: add some more double opcodes to avoid unnecessary lowering

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
gallium: add a cap to enable double rounding opcodes

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
gallium: add shader cap for dldexp/dfracexp support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
mesa/st: add support for new double opcodes

Not having SQRT is assumed to tacitly mean that RSQ is available.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
mesa/st: disable lowering of dops to dfrac when dround is available

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
mesa/st: lower DFRACEXP/DLDEXP when they are not supported

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
gk110/ir: add emission of dadd/dmul/dmad opcodes

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nvc0/ir: fix lowering of RSQ/RCP/SQRT/MOD to work with F64

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nvc0/ir: no instruction can load a double immediate

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nvc0/ir: handle zero and negative sqrt arguments

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nvc0/ir: add support for new TGSI double opcodes

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
nvc0/ir: remove merge/split pairs to allow normal propagation to occur

Because the TGSI interface creates merges for each instruction source
and then splits them back out, there are a lot of unnecessary
merge/split pairs which do essentially nothing. The various modifier/etc
propagation doesn't know how to walk though those, so just remove them
when they're unnecessary.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>