CLK: TI: clockdomain: add support for retrying init

Retry init is needed if clockdomains are registered before the corresponding
clocks are ready. In this case, the clockdomain info is added to a list
which will be processed once the clockdomains for next PRCM module are
processed.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
ARM: PRCM: split PRCM module init to their own driver files

Currently, clock providers coming from CM, PRM, and SCRM are all initialized in
prm_common.c.

Move the DT-match tables to their respective files, and create separate init
functions for each module.

Originally worked on by: Tero Kristo <t-kristo@ti.com>

Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
ARM: OMAP2+: Add CONTROL_MODULE_CORE as a clock provider for DRA7x

In DRA7x SoCs, the CONTROL_MODULE_CORE sub block in the control module has a
few register fields which perform gating or muxing of clocks.

These gate/muxes are generally SoC level clocks entering an IP, which didn't
manage to make it in the clock management related registers for the IP.

Other OMAP SOCs don't seem to have clock related register fields in the control
module.

We create a new table and function to init ctrl-core IPS as clock providers.
This, along with scrm clock providers, are initialized in of_control_init().
We add a compatible string for dra7-ctrl-core in the DT match table.

Signed-off-by: Archit Taneja <archit@ti.com>
ARM: dts: Add ctrl-core DT node for DRA7

Add DT node for the ctrl-core sub module of the DRA7 control module. We map the
CTRL_MODULE_CORE address region up to 0x4a002d60, this region contains register
fields which configure clocks. The remainder of the registers are related to
pad configurations or cross-bar configurations, and therefore aren't mapped.

Signed-off-by: Archit Taneja <archit@ti.com>
ARM: dts: Add dss_deshdcp clock node under dra7-ctrl-core

The DESHDCP clock is required only by the DES-HDCP block within HDMI in DSS.
However, if the clock isn't set before DSS clock domian is enabled, the clock
domain never comes out of idle state.

The DESHDCP clock is enabled/disabled at the DSS boundary by the bit
DSS_DESHDCP_CLKEN in CTRL_CORE_CONTROL_IO_2.

Add dss_deshdcp gate-clock node under dra7-ctrl-core. There are separate bit
fields for enabling and disabling the clock. We just map the enable bit since
this clock doesn't cause any impact if left enabled.

Signed-off-by: Archit Taneja <archit@ti.com>
CLK: TI: Enable dss_deshdcp clock in dra7xx_clk_init

The DESHDCP clock is required only by the DES-HDCP block within HDMI in DSS.
However, if the clock isn't set before DSS clock domian is enabled, the clock
domain never comes out of idle state.

This is because the DSS IP is designed in such a way that if DES-HDCP block
can't transition from idle state, the entire DSS clock domain also cannot
transition from idle to enabled. DES-HDCP block needs the DESHDCP clock
enabled to transition from idle successfully.

We enable the deshdcp clock in dra7xx_clk_init() which happens before omap
hwmods are setup. This clock is effectively a gate clock with the parent as
DSS_L3_GICLK. The parent is an automatically controlled clock by DSS clock
domain and hence doesn't have a clock node associated to it. Since
DSS_L3_GICLK is derived from the OCP clock, we set the dss_deshdcp_clk's
parent as l3_iclk_div.

Leaving this bit enabled doesn't prevent DSS or the system to suspend, and only
a very few flops get this clock all the time. So there is negligible impact.

Signed-off-by: Archit Taneja <archit@ti.com>