ARM: OMAP2+: hwmod: Add a new state to handle hwmods left enabled at init

An hwmod with a 'HWMOD_INIT_NO_IDLE' flag set, is left in
enabled state by the hwmod framework post the initial setup.
Once a real user of the device (a driver) tries to enable it
at a later point, the hwmod framework throws a WARN() about
the device being already in enabled state.

Fix this by introducing a new state '_HWMOD_STATE_ENABLED_AT_INIT'
to identify such devices/hwmods. When the device/hwmod
is requested to be enabled (the first time) by its driver/user,
nothing except the mux-enable and a state change to '_HWMOD_STATE_ENABLED'
is needed. The mux data is board specific and is unavailable during
initial enable() of the device, done by the framework as part of
setup().

A good example of a such a device is an UART used as debug console.
The UART module needs to be kept enabled through the boot, until the
UART driver takes control of it, for debug prints to appear on
the console.

Acked-by: Kevin Hilman <khilman@ti.com>
Acked-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>

Conflicts:
	arch/arm/mach-omap2/omap_hwmod.c
ARM: OMAP: DIMC - Add Digital Mic omap_device

Add the OMAP4 Digital Mic controller.

Signed-off-by: Jorge Eduardo Candelaria <jorge.candelaria@ticom>
Signed-off-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Margarita Olaya Cabrera <magi.olaya@ti.com>

Conflicts:
	arch/arm/mach-omap2/devices.c
ARM: OMAP4: McBSP: Clear rx_irq at probe time

On OMAP4 we have one interrupt line per McBSP port.
At proble time tx, and rx irq value will be -ENXIO,
and only the tx irq will get corrected.
In omap_mcbsp_request if the rx_irq is not 0 we proceed,
and try to request the interrupt, which will fail on
OMAP4 (rx_irq == -6).
To avoid this error, clear the rx_irq at probe time
on OMAP4.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi <at> ti.com>
ARM: OMAP4: Clock: Associate clocks for OMAP temperature sensor

div_ts_ck feeds only the temperature sensor functional clock
and also has a clksel associated (for divider selection). Mapping this
as well as the bandgap_ts_fclk the fclk of temperature sensor in clkdev table,
so a clk_set_rate() on the div_ts_ck in the driver would have the effect of
changing the temperature sensor clock rate indirectly.

Signed-off-by: Keerthy <j-keerthy@ti.com>

authorKeerthy <j-keerthy@ti.com>
Tue, 20 Sep 2011 05:19:25 +0000 (10:19 +0530)
committerSantosh Shilimkar <santosh.shilimkar@ti.com>
Wed, 25 Jan 2012 15:47:41 +0000 (20:47 +0530)
commitaed02698a58cb8b3ae6f00801cb052858fea26ab
tty: omap-serial: Enable omap-serial for all omap2_plus

Remove arch specific enabling and enable omap-serial for all
omap2_plus socs.

Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
ARM: OMAP4+: Adding the temperature sensor register set bit fields

OMAP4460 specific temperature sensor register bit fields are added.
Existing OMAP4 entries are renamed to OMAP4430.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: J Keerthy <j-keerthy@ti.com>
ARM: OMAP4460PLUS: System control module device header

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: J Keerthy <j-keerthy@ti.com>
ARM: OMAP4: System control module device support

Adds system control module device support.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: J Keerthy <j-keerthy@ti.com>
mfd: OMAP4+: System control module driver

Basic system control module driver.

Signed-off-by: J Keerthy <j-keerthy@ti.com>
genirq: Add support for per-cpu dev_id interrupts

The ARM GIC interrupt controller offers per CPU interrupts (PPIs),
which are usually used to connect local timers to each core. Each CPU
has its own private interface to the GIC, and only sees the PPIs that
are directly connect to it.

While these timers are separate devices and have a separate interrupt
line to a core, they all use the same IRQ number.

For these devices, request_irq() is not the right API as it assumes
that an IRQ number is visible by a number of CPUs (through the
affinity setting), but makes it very awkward to express that an IRQ
number can be handled by all CPUs, and yet be a different interrupt
line on each CPU, requiring a different dev_id cookie to be passed
back to the handler.

The *_percpu_irq() functions is designed to overcome these
limitations, by providing a per-cpu dev_id vector:

int request_percpu_irq(unsigned int irq, irq_handler_t handler,
		   const char *devname, void __percpu *percpu_dev_id);
void free_percpu_irq(unsigned int, void __percpu *);
int setup_percpu_irq(unsigned int irq, struct irqaction *new);
void remove_percpu_irq(unsigned int irq, struct irqaction *act);
void enable_percpu_irq(unsigned int irq);
void disable_percpu_irq(unsigned int irq);

The API has a number of limitations:
- no interrupt sharing
- no threading
- common handler across all the CPUs

Once the interrupt is requested using setup_percpu_irq() or
request_percpu_irq(), it must be enabled by each core that wishes its
local interrupt to be delivered.

Based on an initial patch by Thomas Gleixner.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1316793788-14500-2-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
genirq: percpu: allow interrupt type to be set at enable time

As request_percpu_irq() doesn't allow for a percpu interrupt to have
its type configured (it is generally impossible to configure it on all
CPUs at once), add a 'type' argument to enable_percpu_irq().

This allows some low-level, board specific init code to be switched to
a generic API.

[ tglx: Added WARN_ON argument ]

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
genirq: Fix fatfinered fixup really

Putting the argument inside the quote does not really help.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
genirq: Don't allow per cpu interrupts to be suspended

The power management functions related to interrupts do not know
(yet) about per-cpu interrupts and end up calling the wrong
low-level methods to enable/disable interrupts.

This leads to all kind of interesting issues (action taken on one
CPU only, updating a refcount which is not used otherwise...).

The workaround for the time being is simply to flag these interrupts
with IRQF_NO_SUSPEND. At least on ARM, these interrupts are actually
dealt with at the architecture level.

Reported-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1321446459-31409-1-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
ARM: gic: consolidate PPI handling

PPI handling is a bit of an odd beast. It uses its own low level
handling code and is hardwired to the local timers (hence lacking
a registration interface).

Instead, switch the low handling to the normal SPI handling code.
PPIs are handled by the handle_percpu_devid_irq flow.

This also allows the removal of some duplicated code.

Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

Conflicts:
	arch/arm/include/asm/entry-macro-multi.S
	arch/arm/include/asm/localtimer.h
	arch/arm/include/asm/smp.h
	arch/arm/kernel/smp.c
	arch/arm/mach-exynos4/include/mach/entry-macro.S
ARM: gic, local timers: use the request_percpu_irq() interface

This patch remove the hardcoded link between local timers and PPIs,
and convert the PPI users (TWD, MCT and MSM timers) to the new
*_percpu_irq interface. Also some collateral cleanup
(local_timer_ack() is gone, and the interrupt handler is strictly
private to each driver).

PPIs are now useable for more than just the local timers.

Additional testing by David Brown (msm8250 and msm8660) and
Shawn Guo (imx6q).

Cc: David Brown <davidb@codeaurora.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

Conflicts:
	arch/arm/include/asm/hardware/gic.h
	arch/arm/kernel/smp_twd.c
ARM: Make global handler and CONFIG_MULTI_IRQ_HANDLER mutually exclusive

Even when CONFIG_MULTI_IRQ_HANDLER is selected, the core code
requires the arch_irq_handler_default macro to be defined as
a fallback.

It turns out nobody is using that particular feature as both PXA
and shmobile have all their machine descriptors populated with
the interrupt handler, leaving unused code (or empty macros) in
their entry-macro.S file just to be able to compile entry-armv.S.

Make CONFIG_MULTI_IRQ_HANDLER exclusive wrt arch_irq_handler_default,
which allows to remove one test from the hot path. Also cleanup both
PXA and shmobile entry-macro.S.

Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

Conflicts:
	arch/arm/kernel/entry-armv.S
ARM: smp: Add an IPI handler callable from C code

In order to be able to handle IPI directly from C code instead of
assembly code, introduce handle_IPI(), which is modeled after handle_IRQ().

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: GIC: Add global gic_handle_irq() function

Provide the GIC code with a low level handler that can be used
by platforms using CONFIG_MULTI_IRQ_HANDLER. Though the handler is
written in C, the compiled code doesn't feel much slower than its
assembly counterpart (at least with my gcc 4.4.1).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: omap2/3: Add global omap2/3_intc_handle_irq() functions

Provide the OMAP2/3 IRQ code with low level handlers that can be used
by platforms using CONFIG_MULTI_IRQ_HANDLER. Though the handlers are
written in C, the compiled code looks very similar to its assembly
counterpart (at least with my gcc 4.4.1).

Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

Conflicts:
	arch/arm/mach-omap2/irq.c
ARM: GIC: Make MULTI_IRQ_HANDLER mandatory

Now that MULTI_IRQ_HANDLER is selected by all the in-tree
GIC users, make it mandatory and remove the unused macros.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>