Added the VHDL files
Added the C files
rm files
APB slaves testing
APB slaves testing
working input and output buffers
added buffer functionality
Started with a main C-file
Merged Initial-system and LEON_buffered_input_outputs
Cleaned up code
Edited syntax error
Changed read request signal in DAC
APB update
Debug update
New buffers working in simulations
Working system with softcore
working version with a HW UI
More advanced HW UI
Added working bitfile
Merge HW_UI with Master