target-arm: A64: support for AdvSIMD ld/st multiple

This adds support support for the SIMD load/store
multiple category of instructions.

This also brings in a couple of helper functions for manipulating
sections of the SIMD registers.

  * do_vec_get - fetch value from SIMD reg
  * do_vec_set - set value in SIMD reg

which use vec_reg_offset for consistent processing of offsets in an
endian aware manner. There are also additional helpers:

  * do_vec_ld - load value into SIMD
  * do_vec_st - store value from SIMD

Which don't zero extend like the fp variants.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v2 -> v3:
   - use extract32/sextract32 instead of get_bits and get_sbits

v3 -> v4 (ajb):
   - move into new decoder structure
   - use new API for loading temp addr
   - push various variables to local blocks
   - fix semantics of clearing V reg on load
   - tested with risu

v4 -> v5 (ajb):
   - catch more unallocated values
   - add missing returns
   - use do_fp_ld for offset==0 instead of explicit clear_reg

v5 -> v6 (ajb):
   - merge all the various vector helpers into one commit
target-arm: A64: support for SIMD copy operations

This adds support for the all the AdvSIMD copy operations (ARM ARM
3.6.5). These were loosely based on the SUSE originals but are now
considerably simpler. I also brought forward the remainder of the
patches from the Matz tree.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v3 -> v4 (ajb):
   - use ctz32 instead of hand-rolled bit finder
   - catch additional size > 3 unallocated
   - merge INS and DUP into one commit

v5 (ajb):
   - conflicts on re-base

v6 (ajb):
   - remove re-factoring of helper functions

v7 (ajb):
   - merge all copy operations into one commit
   - merge remaining cases from Matz tree
   - catch all unallocated
   - fix get_bits->extract32
   - ensure sign extension correct for !is_q
   - use latest vector access API
target-arm: A64: Add SIMD scalar 3 same ADD/SUB

This adds just Scalar ADD/SUB support to the SIMD scalar 3 same group.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---

v3 -> v4 (ajb):
   - catch Reserved Values
   - don't bother looping, it's just a single D op
translate-a64.c: add a debug helper trace macro

This just makes it easier to drop TRACE_DECODE statements all over the
place instead of fprintfs.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---
rm unused field
scripts/qemu-binfmt-conf.sh: re-factor and clean-up

I was looking to set-up for development but found the script made some
hard-coded assumptions. It doesn't seem the script is used by the
distros but if it had a little more love maybe it would be ;-)

* Add usage() instructions
* Move all registering to a single function
* Check for existence of executable qemu before registering
* Add -d (devel) mode for subscribing in-src tree binaries
* error handling when setting binfmt fails
* add support for aarch64
scripts/qemu-binfmt-check.py: a binfmt checker

This script allows you to check if a given binary will match against any
of the currently registered binfmts on the system.
start of simd ldst single structure decode

It's just a stub for now
linux-user: Implement sendmmsg syscall

Glibc when built for newer kernels assumes that the sendmmsg syscall is available.
Without it, dns resolution simply fails to work.

Wrap the syscall with existing infrastructure so that we don't have a host dependency
on sendmmsg.

Signed-off-by: Alexander Graf <agraf@suse.de>