Revert "microblaze: Extend time for sending chars through mdm IP"

This reverts commit ff231516616304025a32c14f949981164c566ae8.

Not able to replicate problem with MDM uart where this delay
extension was done. Revert this commit to be aligned with the kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Revert "clk: Introduce 'clk_round_rate_nearest()'"

This reverts commit 6761ce9681c317ade70bf41c593b915a1a3af691.

There is no user for this function. Remove it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Revert "watchdog: xilinx: Use xilinx_ prefix"

This reverts commit b44216d55b0a498d01187f83a34bb505c2bf876c.

This change was never sent to mainline.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
watchdog: of_xilinx_wdt: delete non-required instances of include <linux/init.h>

The patch:
"watchdog: delete non-required instances of include <linux/init.h>"
(sha1: 8126334b20d79272a15b5c45053cb76b1e7320be)
removes header from mainline.
Let's sync our tree with mainline version for v3.15-rc1.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
watchdog: of_xilinx_wdt: Simplify timeout calculation

This calculation was chosen based on the mainline discussion
and is used in driver in v3.15-rc1.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
watchdog: xilinx: Enable this driver for Zynq

Enable this driver for Zynq.
Move it to architecture independent Kconfig part.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
zynq: ocmc: Fix documentation according to latest binding

Use ocmc instead of ocm.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
devicetree: Add Xilinx XADC binding documentation

The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx.
The XADC has a DRP interface for communication. Currently two different
frontends for the DRP interface exist. One that is only available on the ZYNQ
family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
on all series 7 platforms and is a softmacro with a AXI interface. This binding
document describes the bindings for both of them since the bindings are very
similar.

Each of them needs:
	* A address range where the registers are mapped
	* An interrupt number for the device interrupt
	* A clock. For the the ZYNQ hardmacro interface this is the modules PCAP
	  clock, for the AXI softmacro it is the AXI bus interface clock.

Additionally the bindings specify whether an external multiplexer is used and in
which mode it is used. The devicetree bindings also describe which external
channels are connected and in which configuration.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
iio:adc: Add Xilinx XADC driver

The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx.
The XADC has a DRP interface for communication. Currently two different
frontends for the DRP interface exist. One that is only available on the ZYNQ
family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
on all series 7 platforms and is a softmacro with a AXI interface. This driver
supports both interfaces and internally has a small abstraction layer that hides
the specifics of these interfaces from the main driver logic.

The ADC has a couple of internal channels which are used for voltage and
temperature monitoring of the FPGA as well as one primary and up to 16 channels
auxiliary channels for measuring external voltages. The external auxiliary
channels can either be directly connected each to one physical pin on the FPGA
or they can make use of an external multiplexer which is responsible for
multiplexing the external signals onto one pair of physical pins.

The voltage and temperature monitoring channels also have an event capability
which allows to generate a interrupt when their value falls below or raises
above a set threshold.

Buffered sampling mode is supported by the driver, but only for AXI-XADC since
the ZYNQ XADC interface does not have capabilities for supporting buffer mode
(no end-of-conversion interrupt). If buffered mode is supported the driver will
register two triggers. One "xadc-samplerate" trigger which will generate samples
with the configured samplerate. And one "xadc-convst" trigger which will
generate one sample each time the CONVST (conversion start) signal is asserted.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
hwmon: Remove ancient xadc driver

There is new in in drivers/iio/adc/xilinx-xadc*.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
gpu: drm: xylon: Removed unused header

Removed unused adv7511 header from Xylon DRM connector.

Signed-off-by: Davor Joja <davorjoja@logicbricks.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
gpu: drm: xylon: Fixed function return type

Fixed function return type in Xylon DRM logicvc.
Bpp value can only be zero or positive value.
Reported by Xilinx review.

Signed-off-by: Davor Joja <davorjoja@logicbricks.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
gpu: drm: xylon: Fixed function return type

Fixed structure member and function return type in Xylon DRM plane.
Bpp value can only be zero or positive value.
Reported by Xilinx review.

Signed-off-by: Davor Joja <davorjoja@logicbricks.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
gpu: drm: xylon: Removed crtc get bpp function

Removed crtc get bpp function.
Moved crtc check format function to different place to keep functionality
grouping within Xylon DRM crtc.

Signed-off-by: Davor Joja <davorjoja@logicbricks.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
gpu: drm: xylon: Updated crtc get parameter function

Xylon DRM crtc get param function is updated to provide all buffer
parameters.
Header file defines replaced with enum type.

Signed-off-by: Davor Joja <davorjoja@logicbricks.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
gpu: drm: xylon: Updated top driver get bpp functionality

Changed bpp variable type in Xylon DRM driver.
Updated getting of bpp value with new functionality.

Signed-off-by: Davor Joja <davorjoja@logicbricks.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
gpu: drm: xylon: Changed logicvc define to enum

Replaced Xylon DRM logicvc various hw defines with enum types.

Signed-off-by: Davor Joja <davorjoja@logicbricks.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
gpu: drm: xylon: Changed plane operation defines to enums

Replaced Xylon DRM plane operation defines with enum types.

Signed-off-by: Davor Joja <davorjoja@logicbricks.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
gpu: drm: xylon: Removed unneeded structure and its use

Removed unneeded structure in Xylon DRM logicvc.
Replaced removed structure variable with plain integer variable.

Signed-off-by: Davor Joja <davorjoja@logicbricks.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
gpu: drm: xylon: Fixed variable and function argument types

Fixed Xylon DRM logicvc main structure variable types according to its usage
and sorted accordingly.
Fixed function argument type to be as hw register width.

Signed-off-by: Davor Joja <davorjoja@logicbricks.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>