[Hexagon] Fixing broken test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223704 91177308-0d34-0410-b5e6-96231b3b80d8
[PowerPC] Don't use a non-allocatable register to implement the 'cc' alias

GCC accepts 'cc' as an alias for 'cr0', and we need to do the same when
processing inline asm constraints. This had previously been implemented using a
non-allocatable register, named 'cc', that was listed as an alias of 'cr0', but
the infrastructure does not seem to support this properly (neither the register
allocator nor the scheduler properly accounts for the alias). Instead, we can
just process this as a naming alias inside of the inline asm
constraint-processing code, so we'll do that instead.

There are two regression tests, one where the post-RA scheduler did the wrong
thing with the non-allocatable alias, and one where the register allocator did
the wrong thing. Fixes PR21742.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223708 91177308-0d34-0410-b5e6-96231b3b80d8
[PowerPC]Activate FeatureVSX for the Power target

This change activates FeatureVSX for Power 7 and Power 8 in PPC.td.

http://reviews.llvm.org/D6570


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223709 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Adding any8, all8, and/or/xor/andn/orn/not predicate register forms, mask, and vitpack instructions and patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223710 91177308-0d34-0410-b5e6-96231b3b80d8