verilog: Ignore preprocessor macros in module port declaration

Support the following port declarations:

module mod (
    `ifdef DEF
    input wire a,
    `else
    input wire b,
    `endif
    output wire c
    );
Merge pull request #194 from vhda/verilog/fix-macros-in-portdecl

verilog: Ignore preprocessor macros in module port declaration