Merge pull request #8 from hansiglaser/master

Added support for notif0/notif1 primitives
Merge pull request #9 from hansiglaser/master

Added support for include directories with the new '-I' argument of the 'read_verilog' command
Some minor documentation fixes
Merge pull request #10 from hansiglaser/master

fixed Verilog parser filename and line numbering issue with include files
Added edif backend (still under construction)
Added correct encoding of identifiers in EDIF backend
More explicit integer output in verilog backend
Added simple xilinx7 technology mapping files
Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)
Improved edif backend
Encode large (>32 bits) parameters as hex string in edif backend
Added -selected option to various backends
Merge branch 'master' of github.com:cliffordwolf/yosys
Added spice backend
Added spice testbench to techlibs/cmos
Updated manual
Moved common techlib files to techlibs/common
A couple of small fixes in SPICE backend
Added BLIF backend
Added additional options to BLIF backend