cores: add verilog_utils core

The idea behind the verilog_utils core is to gather convinience
functions in one place, that other cores can pull in and use.
As a start, it contains an implementation of clog2, for
tools that doesn't yet have proper support for $clog2
(most notable ISE < 14.1).
Also functions for find first/last one are included.
wb_intercon: use verilog_utils

Takes the recently added verilog_utils into use,
which make the implementation slightly cleaner.
By this, a bug in the $clog2 implementation in ISE < 14.1
is resolved.
And a workaround for a bug in verilator is removed
(more recent version of verilator than where the bug was
present, is needed for other reasons anyway).
wb_intercon: fix single slave connections

When a master only had a single slave, there would be no
connection made between the master and slave.
The reason was that _gen_mux was never called on
master.slaves == 1, even though _gen_mux has code to handle
the condition.
A note on that though, a wb_mux will still be instantiated,
but this is IMO correct behaviour instead of hard connect the
wires between the master and the slave, since additional
address matching logic will be added with wb_mux.
add verilator_tb_utils core

The verilator_tb_utils core consist of the non-or1200 specific
part of the or1200-generic verilator test bench and
wraps them in a reusable C++ class.

The biggest difference is probably the argument parsing,
the custom strcmp parsing have been replaced with argument
parsing from the argp library.
The argp library has support for parent/child parser,
and the VerilatorTbUtils class parser is intended to be
used as a child parser, i.e. the arguments can be
extended by the main test bench that instantiates the class.
or1200-generic: use verilator_tb_utils

This removes all non-or1200 specific code that is now
implemented in verilator_tb_utils instead.

An (almost) empty argument parser template is added,
which only purpose right now is to initiate the child parser
in verilator_tb_utils.

A signal handler is also added to catch ctrl-c.
Merge branch 'wb_intercon' of github.com:skristiansson/orpsoc-cores into master
Merge branch 'verilog_utils' of github.com:skristiansson/orpsoc-cores into master
wb_intercon: allow single master/slaves

The result of clog2(1) = 0, which will result in
master/slave_sel bit vectors of [-1:0].
Threat the special case of num_masters/slaves == 1,
so a bit vector [0:0] is created.
wb_intercon: fix multiple masters to single slave connections

The commit: 5f7cbf7e77a6d54641efc4c832628265a605d1e2
'wb_intercon: fix single slave connections'
took care of the case with a single master connected to
a single slave. The case with several masters connected
to a single slave was however oversighted.
cores/mor1kx: add mor1kx_monitor

This enables the use of mor1kx_monitor and the associated
plusargs.
systems: add mor1kx-generic

Heavily based on the or1200-generic system, the mor1kx-generic
system serves the same kind of purpose - to provide a minimal
simulation platform, but for mor1kx instead of or1200.
verilator_tb_utils: change all 'times' to uint64_t

Franck Jullien reported that unsigned long is not a valid argument
for tfp->dump() on 32-bit machines.
This changes all 'time' (cycles, really) references to uint64_t.
cores: remove name from [vpi] sections

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Update description
mor1kx: Add new LRU module for caches

The current mor1kx master has a new file for the multiple way caches.
cores: add mt46v16m16p DDR memory model

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
cores: add wb_altera_ddr_wrapper

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
cores: add ps2 core

This core is originally from opencores, but have been rewritten
in verilog and had a lot of bugfixes added to it.
Due to this, it makes more sense to add this as a whole core
instead of pulling in the original and adding the complete rewrite
as a patch.
systems: add atlys board port

OpenRISC system for Digilent Atlys development board.
Basically lifted 'as is' from the orpsocv2 port at:
git://git.openrisc.net/stefan/orpsoc

TODO:
 - Rewrite dvi_gen (currently a hacked up Xilinx whitepaper)
 - Clean up the Xilinx MIG memory controller wrapper
   (and possibly generate the MIG with coregen on fly)
 - General cleanup and de-orpsocv2-fication
Merge pull request #48 from skristiansson/verilator_tb_utils

verilator_tb_utils: change all 'times' to uint64_t