Started adding PCIe core instance

This commit has the Clarity core (PCIe + refclk) installation in
wiggle.v. The net names in the instance are partially sorted to match
the PCIe endpoint user’s guide (for readability).
Still sorting PCIe instance

Sorted receive TLP nets
More sorting

Sorted Control and Status nets
Added PCIe instantiation

Finished sorting the PCIe instantiation ports and added default values
and physical pin connections.
Corrected Verilog compile errors

Theses errors were identified by Lattice. It turns out that when the
Diamond parser detects errors in the top level file it automatically
changes the top-level to something else (in this case the Clarity SBX
file).
Corrected PERESTn pin assignment
Updated bank voltages based on the schematic
Set configuration voltage to 3.3V

Without this setting setting Bank 8 to 3.3V failed.
Re-added IO_TYPE assignment for PERSTn

Apparently all three settings are required (bank voltage, sysconfig
voltage, and io_type)
Added SBX (PCIe core)