src/chip/ad9510*: add pll configuration
src/chip/si570.cpp: small print fixes
src/*/platform/*: add new delay values for fmc250m
src/fmc_config_130m_4ch.cpp: change si570 frequency and ad9510 pll
src/fmc_config_250m_4ch_passive.cpp: comment out big testing sleep
src/chip/ad9510.cpp: change PLL divider and output mux pin
src/fmc_config_130m_4ch_crystek.cpp: add support for crystek oscillator
src/chip/ad9510.cpp: change ad9510 clock port
src/fmc_config_130m_4ch.cpp: add some Si571 clock frequencies
src/fmc_config_130m_4ch_crystek.cpp: add simple main file to support crustek clock gen
src/fmc_config_130m_4ch_ext_clk_no_pll.cpp: add simple main file to support external clock with no PLL
src/Makefile*: update Makefiles
src/fmc_config_130m_4ch.cpp: add more si571 configurations
src/chip/ad9510.cpp: change divider to 10 and fix assertions

We should heave a generic way of changing these values
without recompiling and altering the source code!
src/chip/ad9510.cpp: fix divider comments
src/chip/ad9510.h: add PLL status mask
src/include/data.h: add support for different addressing

We can have WB peripherals that are addressed in BYTE or
WORD granularity
src/include/plat_opts.h: add header to select WB addressing
src/interface/*: change SPI and I2C to use chosen WB granularity
src/reg_map/*: add 2 distinct address map

We have different register maps for two different
test firmwares