debugger: fix lua includes.

Our include paths should be pulled in by cmake, so we don't need the
explicit lua5.2 dir.
sim: indicate which items are cacheable.

For implementing the data cache we need to know what peripherals are
cacheable or not.  For instruction fetches everything is cacheable, but
for data accesses only ram/rom is cacheable.  Rather than hard code that
into the load/store helpers, provide a helper for getting the
cacheability of an address.

Note that later once an MMU is implemented this will still be the
canonical source - a page marked as cacheable won't be cacheable if the
peripheral is not really cacheable.
sim: implement data cache support.

The data cache is direct mapped and only allocates on reads.  The
tracking is the same as for the instruction cache, just with the
addition of a dirty bit which indicates the line has been written to
since linefill and needs to be written back later.
tests/selfmod: ensure we partially exercise the dcache.

Forcibly do a linefill of the data cache for it to then be overwritten.
This will make sure that we do actually handle dirty lines and debug
synchronization correctly.
config/keynsham: add a 8KB data cache.
debugger: update cpuid() for data cache.
rtl/debug: add an explicit debug_en signal.

We want to split operations from normal execution and debug so there
isn't any confusion - for example memory accesses completion should only
go to the debug unit rather than fetch unit else we can end up advancing
the PC incorrectly when finishing a debug access.
oldland_cache: rework cache to allow writes.

Rework the cache so that it can be used as a data cache and hook it up
to the CPU.  This implements a simple data cache but does not yet track
dirty lines, only valid.  This means that when evicting a line due to a
conflict may cause the line to be written back even if not modified.
bootrom: sync caches after loading.

The data cache needs to be flushed and the instruction cache invalidated
to make sure the caches are coherent with memory.
keynsham_soc: merge data read/write busses.

Rather than having separate busses for data read/write, perform bitwise
OR onto a single bus.
rtl/cpu: include unused pin definitions in icache cell.
rtl: rename oldland_execute to match the module name.
rtl/dc_ram: disable verilator warning.

This is safe as we only write from one domain at a time.
verif: silence verilator lint warnings.
keynsham/sdram: don't have ack depend on cs.

cs is combinational and we don't want ack to be dependent on it (or else
there can be combinational loops).
rtl/timer: wire-OR all ack signals.

Having the ack signals wire-OR'd means that they don't change when cs
changes - they need to stay stable for a whole cycle.
rtl/sdram: update submodule.